Ryoji Kosugi

Excellent effects of hydrogen postoxidation annealing on inversion channel mobility of 4H-SiC MOSFET fabricated on (11 2 0) face

Effects of hydrogen postoxidation annealing (H/sub 2/ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112~0) face have been investigated. As a result, an inversion channel mobility of 110 cm/sup 2//Vs was successfully achieved using H/sub 2/ POA at 800/spl deg/C for 30 min. H/sub 2/ POA reduces the interface trap density by about one order of magnitude compared with that without H/sub 2/ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H/sub 2/ POA. In addition, 4H-SiC MOSFET with H/sub 2/ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm/sup 2//Vs.

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500/spl deg/C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1/spl times/10/sup 17/ cm/sup -3/, the optimum depth was found to be 0.2 /spl mu/m. Under this condition, a channel mobility of 140 cm/sup 2//Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide.

Strong dependence of the inversion mobility of 4H and 6H SiC(0001) MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (/spl rho/(H/sub 2/O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also /spl rho/(H/sub 2/O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm/sup 2//Vs for 4H and 95 cm/sup 2//Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a /spl rho/(H/sub 2/O) of 50%.

Correlation between channel mobility and shallow interface traps in SiC metal–oxide–semiconductor field-effect transistors

The shallow interface trap density near the conduction band in silicon carbide (SiC) metal–oxide–semiconductor (MOS) structure was evaluated by making capacitance–voltage measurements with gate-controlled-diode configuration using the n-channel MOS field effect transistors (MOSFETs). The close correlation between the channel mobility and the shallow interface trap density was clearly found for the 4H- and 6H-SiC MOSFETs prepared with various gate-oxidation procedures. This result is strong evidence that a significant cause of the poor inversion channel mobility of SiC MOSFETs is the high density of shallow traps between the conduction band edge and the surface Fermi level at the threshold.

Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO2/4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm2/Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO2 may be responsible for the reduced trap density and enhanced channel mobility.

Relationship between channel mobility and interface state density in SiC metal–oxide–semiconductor field-effect transistor

Temperature dependence of threshold voltage in n-channel SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from −150 to 150 °C and the number of the interface states present within the energy range of 0.2–0.4 eV from the conduction band edge energy Ec. This relationship revealed that the interface state profile near Ec in n-channel SiC MOSFETs can be represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility and the interface state profile also suggested that the interface states within the energy range of 0.2–0.4 eV from Ec have little influence on the channel mobility.

First experimental demonstration of SiC super-junction (SJ) structure by multi-epitaxial growth method

A super-junction (SJ) device has been developed to improve the trade-off relationship between the breakdown voltage (VBD) and specific on-resistance in unipolar devices. Si-SJ devices are now widely used, and the effect of the SJ structure is also expected in SiC devices. Fundamental processes for fabricating SJ structures by using a multi-epitaxial (ME) growth method have been developed, where the epitaxial growth and MeV-class implantation steps are alternately repeated. Two types of test elemental groups (TEGs) were formed on the same wafer for evaluation of VBD and the specific resistivity of the drift layer (Rdrift). The measured VBD was 1545 V, which was higher than that of the SiC theoretical limit by 670 V, and a value of Rdrift (including the substrate resistance) of 1.06 mΩ·cm2 was obtained.

Development of SiC Super-Junction (SJ) Device by Deep Trench-Filling Epitaxial Growth

We have tried to fabricate a super junction (SJ) structure in SiC semiconductors by the trench-filling technique. After the deep trench formation by dry etching, epitaxial layer is grown over the trench surface. Doping profile of the embedded p-type epitaxial region between the trenches is evaluated by a scanning spreading resistance microscopy (SSRM). The SSRM result reveals that the doping profile is not uniform and there exists a low concentration region along the trench side-wall. Based on the SSRM result, two-dimensional device simulations are performed using pn-type test structures with the non-uniform SJ drift layer. The simulation result shows that blocking voltage of the test structure can be optimized and becomes comparable to that of the ideal one by adjusting the concentration design of the embedded layer to balance the total charge in SJ structure.

Development of SiC Super-Junction (SJ) Devices by Multi-Epitaxial Growth

Super-junction (SJ) devices have been developed to improve the trade-off relationship between the blocking voltage (VBD) and specific on-resistance in unipolar power devices. This SJ structure effect is expected in SiC unipolar devices. Multi-epitaxial growth is a known fabrication method for SJ structures where epitaxial growth and ion implantation are repeated alternately until a certain drift-layer thickness is achieved. In this study, we fabricated two types of test elemental groups with an SJ structure to evaluate the breakdown voltage (VBD) and specific resistivity of the drift layer (Rdrift). Experimental results show that VBD exceeded the theoretical limit of the 4H-SiC by 300V, and Rdrift agreed well with the estimated value from the device simulation. The beneficial effects of the SJ structure in the SiC material on VBD and Rdrift were confirmed for the first time.

Thermal oxidation of (0001) 4H-SiC at high temperatures in ozone-admixed oxygen gas ambient

The method of oxidation by atomic oxygen has been developed for gate oxide formation in SiC metal–oxide–semiconductor (MOS) devices. Ozone (O3)–admixed oxygen (O2) gas is introduced into the cold-wall oxidation furnace, where atomic oxygen in a ground state is formed by thermal decomposition of O3 molecules at elevated sample temperatures. The growth rate of oxide in the O3-admixed gas shows a maximum at around 666.4 Pa and 950–1200 °C, whereas the rate in pure O2 gas is negligible below 6664.5 Pa. Interface trap density (Dit) of the MOS capacitors fabricated using atomic oxygen strongly depends on the oxidization temperature; oxidation at 1200 °C results in significant reduction of Dit in comparison with that at 950 °C.