Ryuichi Oikawa

Package substrate built-in three-dimensional distributed matching circuit for high-speed SerDes applications

This paper proposes a new method to resolve the on-die capacitance issue of the high-seed SerDes (serializer-deserializer). This issue can be resolved by incorporating a three-dimensionally controlled distributed impedance matching circuit into the package substrate. The distributed matching circuit has been applied to the 6.25 Gbps SerDes device by using a conventional build-up substrate as a package substrate. As a result, the return loss showed a ~6 dB (~200%) improvement as well as showing a better signal waveform than standard 50 Ohm package design. Because this method does not require any additional manufacturing technology other than conventional build-up substrate, the cost of high speed (Gbps) communication devices can be reduced and also extend conventional technology to the even higher speed devices.

A low-cost wire-bonding package design with package built-in three-dimensional distributed matching circuit for over 5Gbps SerDes applications

The package built-in three-dimensional distributed matching circuit[1], which had been developed for FCBGA , has been extended to the low-cost wire-bonding packages. The two-metal layer package designed for 6.4Gps SerDes (Serializer-Deserializer) achieved a ∼4dB return loss improvement as well as better signal waveform compared to the normal 50-Ohm design. In addition, signal-power coupling effect on the high-speed SerDes device has been analyzed for the first time based on the full-wave, full-3D, signal-power-combined electromagnetic analysis, which suggests that the power integrity design substantially affects the common mode noise generation inside the wire-bonding packages of high-speed SerDes devices.

A low-cost QFP design for over 8Gbps SerDes applications with inductive return path co-planar waveguide built into the lead frame

In order to overcome large impedance discontinuities and crosstalk issues observed in the low-cost QFP, a new design scheme called inductive return path co-planar waveguide is proposed, which distributed circuit structure works a passive impedance equalizer at the same time reduces crosstalk necessary to achieve over-10Gbps signal transmission. The proposed design scheme has been applied to an exposed die-pad type TQFP, which has achieved successful 12.8Gbps differential signal transmission. Because this distributed circuit design needs only a small layout space, it is suitable to achieving compact and low-cost consumer device packaging. Additionally this design scheme is applicable not to only the TQFP but also to normal QFP.

A broadband SSO modeling for a weak signal return-path system based on the large-scale signal-power combined three-dimensional full-wave BEM solver model

An over-2Gbps SSO analysis for a low-cost wire-bonding type BGA package with 32bit DDR interface is demonstrated. The analysis is based on the true transistor-level signal-power integrity simulation, a large-scale, full-wave, full-three dimensional BEM field solver package model and return-path decomposition method which eliminates artificial return-path discontinuities. The simulation results suggests that in the weak return-path system, such as wire-bonding type package, the system performance is mainly dominated by the signal channel design rather than the power supply design in over 2Gbps region, which includes the power supply acting as a secondary signal return-path rather than noise source. The power supply design should be mainly focused on the main driver/pre-driver power supply noise interference in those systems.

New signal skew cancellation method for 2 Gbps transmission in glass and organic interposers to achieve 2.5D package employing next generation high bandwidth memory (HBM)

Glass and organic interposers have been expected as strong alternatives to Si interposer (Si-IP) from the viewpoint of package cost reduction. A 2.5-D package that consists of HBM Gen 2 and a logic die placed side by side on a glass or an organic interposer by flip-chip bonding (FCB) is studied. We have successfully developed a new signal skew cancellation method by controlling Cu plated through via (PTV) locations, interposer wirings, and signal pin order. It is confirmed that more than 2Gbps, HBM Gen 2 data rate, of signal transmission is doable on the interposers designed by the new method by SPICE simulation. It is also demonstrated that the new method reduces the number of necessary conductive layers, providing a low-cost 2.5-D package solution.

A high-speed, long-reach signal design challenge for 2.5-D LSI based on a low-cost silicon interposer and a large-scale SSO analysis

A new signal line structure based on a single-sided low-cost silicon interposer is proposed, which extends high-speed signal reaching distance over 16 mm. The proposed signal structure and design scheme are applied to a full-function 2.5-D LSI product that has originally been developed based on a wide-pin pitch organic substrate. Despite a long signal length, the fabricated LSI has successfully worked with a large enough operation margin. This paper also discusses an SSO model reduction technique that enables the analysis of hundreds of parallel signal lines in a practical period. The design method presented in this paper can further extend the range of the low-cost silicon interposer application beyond the usage for wide-I/O or HBM (high bandwidth memory).

A Feasibility Study on 100Gbps-Per-Channel Die-to-Die Signal Transmission on Silicon Interposer-Based 2.5-D LSI with a Passive Digital Equalizer

This paper proposes a passive equalizer that works as a digital filter compensating a large ISI (inter-symbol interference) of 100 Gbps or faster signal on high-loss signal lines on silicon interposers. The equalizer, which discretizes input signal through multiple signal reflection, is implemented on a silicon interposer, without need for circuit area and power supply on LSI (large-scale integration) die. In addition to the passive equalizer, a small amplitude, low impedance driver and a non-terminated receiver are employed for minimizing power consumption at the same time maximizing the signal amplitude at the receiver. A signal integrity simulation based on those design techniques has confirmed that 100 Gbps, NRZ (non-return-to-zero) signal transmission is possible over ~1/2-inch signal line on silicon interposer, as long as I/O parasitic load is sufficiently small. This result suggests the possibility of bandwidth expansion of the silicon interposer-based 2.5-D LSIs by decade times in the near future.

An efficient modeling of the multi-gigabit SSO interference to the pre-driver in the weak power supply system based on the charge exchange domain partitioning technique with intentionally utilizing high power supply impedance

A mitigation of the multi-gigabit SSO noise interference from the I/O buffer to the pre-driver in a DDR4 interface is demonstrated by utilizing a parasitic low-pass noise filter inside the low-cost wire-bonding packages. By optimizing the mutual inductance between I/O drivers and pre-drivers power supplies, the on-die decoupling capacitance of the 32bit DDR4 interface operating at 2133Mbps has been successfully reduced by 66–75% with keeping signal quality. A scaling issue in the SSO noise interference analysis is also addressed in this study by employing a domain partitioning technique based on whether individual power supply is closed or open system on the electrical charge. The design study has demonstrated the advantage of the low-cost wire-bonding packages when used for multi-gigabit single-ended interface, which also suggests the design direction and possibility of the over-2Gbps DDR interface with the wire-bonding packages.