Takuo Funaya

A novel ultra-thin package for embedded high-pin-count LSI supported by Cu plate

We have developed a thin, low-thermal-resistance LSI package by embedding a high-pin-count LSI chip into ultra-thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 µm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics, smaller than 82 µm in the temperature range from −55 to +260 °C. Low thermal resistance of 10.8 °C/W is achieved at a wind velocity of 0 m/s, which is also comparable to that of the FCBGA with a large heat sink. We have successfully demonstrated the functions of this package using an LSI tester and personal-computer-like system board. It has also passed a 600-cycle package-level thermal cycle test.

Electrical design and demonstration of an embedded high-pin-count LSI chip package

Design techniques for an ultra-thin LSI package embedding a high-pin-count LSI chip in the thin package substrate have been developed to achieve the excellent electrical performance, as well as low warpage and high heat removal. The embedded chip package we designed is 27 mm by 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip chip ball grid array (FCBGA) package using the same chip. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network (PDN) is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick copper plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. Our design for a product LSI chip with approximately 1,500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip.

Diamond bit cutting as alternative to polymer patterning for 3D interconnections technologies

We report on the use of the diamond bit cutting technique in the fabrication of polymer embedded Cu interconnects. This fabrication technique is an attractive alternative to standard patterning techniques used to fabricate such interconnect structures e.g. lithographic, dry etching or laser patterning.

Embedded Active Packaging Technology for High-Pin-Count LSI With Cu Plate

We have developed a thin, reliable, low-thermal-resistance LSI packaging technology by embedding a high-pin-count LSI chip into thin build-up layers supported by Cu plate. The embedded LSI chip is a microprocessor with approximately 1500 pads and a thickness of 50 μm, and it is completely laminated by the first build-up epoxy resin. The total package thickness is only 0.71 mm including a 0.5-mm-thick Cu plate for cooling, which is much thinner than the conventional flip chip ball grid array (FCBGA) package with a heat sink. Our package shows excellent warpage characteristics of only 34 μm at room temperature for 27 × 27 mm2 in size. It is also possible to reduce the total package thickness to 0.46 mm by etching the Cu plate to half thickness, with keeping the warpage increase up to 117 μm. Low thermal resistance of 10.8°C/W is achieved for the packages with 0.5-mm-thick Cu plate at a wind velocity of 0 m/s, which is almost comparable to that of an FCBGA with a large heat sink. We have successfully demonstrated the functions of our packages using an LSI tester and personal-computer-like system board. They have also passed a 1000-cycle package-level thermal cycle test.

Alternative patterning techniques enabling fine pitch interconnection on topography surfaces

We report on the fabrication of small pitch (20 µm) interconnection structures based on Cu pillars embedded in polymer. Such structures are useful in different applications such as integrated passives and die embedding technologies. To allow the fabrication of such structures, we made use of the diamond bit cutting and dry etching techniques as alternatives to the currently used lithographic process. This latter did not allow targeting such aggressive pitches and structures dimensions.

Electrical Design and Techniques for an Embedded High-Pin-Count LSI Chip Package

In order to achieve the excellent electrical performance, as well as low warpage and high heat removal, electrical design techniques for an ultrathin large-scale integration (LSI) package embedding a high-pin-count LSI chip in the thin package substrate have been developed. The embedded chip package we designed is 27 mm × 27 mm in size and 0.71 mm in thickness with a heat spreader. The package is attained with only three metal layers against the six metal layers of the product flip-chip ball grid array package using the same chip, even though the package size is the same. Although the two power plane layers have been removed from the substrate, the low impedance of the power distribution network is achieved by utilizing many bundles of fine vias. A 0.5-mm-thick Cu plate attached to the LSI chips backside provides the signal return path, and contributes to the flatness of this thin package. It also effectively removes heat from the chip. In addition, it functioned as a shield component and results in electromagnetic interference suppression. Our design for a fully operative LSI chip with approximately 1500 pins demonstrates excellent electrical performance as well as small thickness, low warpage, and a high rate of heat removal. Function tests using an LSI tester and a PC-like system board successfully demonstrate the outstanding performance of the LSI chip. Finally, the advantage of a heat sink connected to ground plane of the package is discussed. It is found that, for excellent near-field noise suppression effects, the heat sink must be connected to the ground plane.

Ultra thin die embedding technology with 20μm-pitch interconnection

A novel approach is presented for polymer die embedding and 3D stacking technology, applicable to 3D LSI packaging with consideration to future die specifications. Two main parts are described here; a newly developed die thinning process and an integration process employing via opening by deep reactive ion etching (DRIE). The target minimum pad pitch on embedded dies was 20 µm, considering the finest pad pitch in the next 5 to 10 years. Thin dies embedded in polymer allow for the use of narrow-pitch copper pillars beside the dies for vertical conductive connections. 20 µm-pitch pads on approximately 15 µm-thick die were successfully connected using such 3D interconnections to a base wafer, and confirmed by electrical measurements.