Ryo Mori

A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

An in situ measurement scheme for generating supply-noise maps, which can be conducted while running applications in product-level LSIs, was developed. The design of the on-chip voltage sampling probe is based on a simple ring oscillator, which converts local supply difference between VDD and VSS to oscillation-frequency deviation. High measurement accuracy is achieved by off-chip digital signal processing and calibration. This scheme was used to successfully measure 69-mV local supply noise with 5-ns time resolution in a 3G-cellular-phone processor. It will thus help in designing power-supply networks and in visually verifying the quality of a power supply

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are as follows. 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2 GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28 nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), resulting in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40 mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC voltage drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

Early stage chip/package/board co-design techniques for system-on-chip

With the advancements in semiconductor process technologies in recent years, many circuits are mounted on small dies and the number of interface pins has rapidly increased. The demand for smaller chip/package sizes has come about in order to reduce costs. This paper describes the early stage chip/package/board co-design techniques which reduce chip and package size by cutting down the number of PDN (Power Distribution Network) pads/balls and improve the routability of the package. The key techniques are early stage package/board properties estimation and IR drop estimation. These techniques have a good degree of accuracy even at early stage estimation and a short processing time. From experimental result using a 45-nm process TEG (Test Element Group) chip, the package size was reduced by 21.5%, and the chip size was reduced by 16.4% in comparison with the original design which was designed conventional techniques. The experimental result demonstrates the validation of the proposed techniques.

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermal-compression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores

The worldwide demand for high-performance mobile or car infotainment application processors (AP) is increasing. This demand coexists with the need for low power to achieve long battery life and avoid thermal runaway. A heterogeneous CPU configuration is an effective solution. The proposed heterogeneous quad/octa-core AP has a combination of high-performance 2GHz cores and energy-efficient 1GHz cores. The maximum performance in the octa-core configuration is 35600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm HPM process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg). 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling.

Challenges of design and packaging for 3D stacking with logic and DRAM dies

A Wide IO DRAM controller chip with Through Silicon Via (TSV) technology is implemented. Test circuitry for prebonding TSV tests are embedded in between the fine pitch TSVs. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We also develop a 3D stacked flip chip assembly process with void less underfill enabled by Non Conductive Film (NCF). 12.8 GB/s operation is achieved, while IO power was reduced by 89% compared to LPDDR3.

Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor

We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital noise monitor. We achieved 12.8 GB/s operation, while IO power was reduced by 89 % compared to LPDDR3.

A high-speed, long-reach signal design challenge for 2.5-D LSI based on a low-cost silicon interposer and a large-scale SSO analysis

A new signal line structure based on a single-sided low-cost silicon interposer is proposed, which extends high-speed signal reaching distance over 16 mm. The proposed signal structure and design scheme are applied to a full-function 2.5-D LSI product that has originally been developed based on a wide-pin pitch organic substrate. Despite a long signal length, the fabricated LSI has successfully worked with a large enough operation margin. This paper also discusses an SSO model reduction technique that enables the analysis of hundreds of parallel signal lines in a practical period. The design method presented in this paper can further extend the range of the low-cost silicon interposer application beyond the usage for wide-I/O or HBM (high bandwidth memory).

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce Vmin degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.