S. Baron

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset.

The GBT-SerDes ASIC prototype

In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBT- SerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while oper- ating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed- Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

Implementing the GBT data transmission protocol in FPGAs

The GBT chip [1] is a radiation tolerant ASIC that can be used to implement bidirectional multipurpose 4.8Gb/s optical links for high-energy physics experiments. It will be proposed to the LHC experiments for combined transmission of physics data, trigger, timing, fast and slow control and monitoring. Although radiation hardness is required on detectors, it is not necessary for the electronics located in the counting rooms, where the GBT functionality can be realized using Commercial Off-The-Shelf (COTS) components. This paper describes efficient physical implementation of the GBT protocol achieved for FPGA devices on Altera and Xilinx devices with source codes developed in Verilog and VHDL. The current platforms are based on Altera StratixIIGX and Xilinx Virtex5. We will start by describing the GBT protocol implementation in detail. We will then focus on practical solutions to make Stratix and Virtex transceivers match the custom encoding scheme chosen for the GBT. Results will be presented on single channel occupancy, resource optimization when using several channels in a chip and bit error rate measurements, with the only aim to demonstrate the ability of both Altera and Xilinx FPGAs to host such a protocol with excellent performances. Finally, information will be given on how to use the available source code and how to integrate GBT functionality into custom FPGA applications. I. GBT PROTOCOL PRESENTATION

The Gigabit Link Interface Board (GLIB), a flexible system for the evaluation and use of GBT-based optical links

The Gigabit Link Interface Board (GLIB) is an evaluation platform and an easy entry point for users of high speed optical links in high energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory to control, triggering and data acquisition from remote modules in beam or irradiation tests. The GLIB is an FPGA-based Advanced Mezzanine Card (AMC) conceived to serve a small and simple system residing either inside a Micro Telecommunications Computing Architecture (μTCA) crate, or on a bench with a link to a PC. This paper presents the architecture of the GLIB, its features as well as examples of its use in different setups.

Test bench development for the radiation Hard GBTX ASIC

This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements a bidirectional 4.8 Gb/s link between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional testing of the GBTX and to evaluate its performance in a radiation environment, by conducting Total Ionizing Dose and Single-Event Upsets tests campaigns.

Recent aging studies for the ATLAS transition radiation tracker

The transition radiation tracker (TRT) is one of the three subsystems of the inner detector of the ATLAS experiment. It is designed to operate for 10 yr at the LHC, with integrated charges of /spl sim/10 C/cm of wire and radiation doses of about 10 Mrad and 2/spl times/10/sup 14/ neutrons/cm/sup 2/. These doses translate into unprecedented ionization currents and integrated charges for a large-scale gaseous detector. This paper describes studies leading to the adoption of a new ionization gas regime for the ATLAS TRT. In this new regime, the primary gas mixture is 70%Xe-27%CO/sub 2/-3%O/sub 2/. It is planned to occasionally flush and operate the TRT detector with an Ar-based ternary mixture, containing a small percentage of CF/sub 4/, to remove, if needed, silicon pollution from the anode wires. This procedure has been validated in realistic conditions and would require a few days of dedicated operation. This paper covers both performance and aging studies with the new TRT gas mixture.

The Gigabit Link Interface Board (GLIB) ecosystem

The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments. The major hardware component of the platform is the GLIB Advanced Mezzanine Card (AMC). Additionally to the AMC, auxiliary components are developed that enhance GLIB platforms I/O bandwidth and compatibility with legacy and future triggering and/or data acquisition interfaces. This article focuses on the development of the auxiliary components that together with the GLIB AMC offer a complete solution for beam/irradiation tests of detector modules and evaluation of optical links.

A TTC upgrade proposal using bidirectional 10G-PON FTTH technology

A new generation FPGA-based Timing-Trigger and Control (TTC) system based on emerging Passive Optical Network (PON) technology is being proposed to replace the existing off-detector TTC system used by the LHC experiments. High split ratio, dynamic software partitioning, low and deterministic latency, as well as low jitter are required. Exploiting the latest available technologies allows delivering higher capacity together with bidirectionality, a feature absent from the legacy TTC system. This article focuses on the features and capabilities of the latest TTC-PON prototype based on 10G-PON FTTH components along with some metrics characterizing its performance.

Acceptance tests and criteria of the ATLAS transition radiation tracker

The Transition Radiation Tracker (TRT) sits at the outermost part of the ATLAS Inner Detector, encasing the Pixel Detector and the Semi-Conductor Tracker (SCT). The TRT combines charged particle track reconstruction with electron identification capability. This is achieved by layers of xenon-filled straw tubes with periodic radiator foils or fibers providing TR photon emission. The design and choice of materials have been optimized to cope with the harsh operating conditions at the LHC, which are expected to lead to an accumulated radiation dose of 10 Mrad and a neutron fluence of up to 2middot1014 n/cm2 after ten years of operation. The TRT comprises a barrel containing 52 000 axial straws and two end-cap parts with 320 000 radial straws. The total of 420 000 electronic channels (two channels per barrel straw) allows continuous tracking with many projective measurements (more than 30 straw hits per track). The assembly of the barrel modules in the US has recently been completed, while the end-cap wheel construction in Russia has reached the 50% mark. After testing at the production sites and shipment to CERN, all modules and wheels undergo a series of quality and conformity measurements. These acceptance tests survey dimensions, wire tension, gas-tightness, high-voltage stability and gas-gain uniformity along each individual straw. This paper gives details on the acceptance criteria and measurement methods. An overview of the most important results obtained to-date is also given

GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

The high-energy physics experiments at the CERNs Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.