P. Moreira

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset.

The GBT-SerDes ASIC prototype

In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBT- SerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while oper- ating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed- Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

Implementing the GBT data transmission protocol in FPGAs

The GBT chip [1] is a radiation tolerant ASIC that can be used to implement bidirectional multipurpose 4.8Gb/s optical links for high-energy physics experiments. It will be proposed to the LHC experiments for combined transmission of physics data, trigger, timing, fast and slow control and monitoring. Although radiation hardness is required on detectors, it is not necessary for the electronics located in the counting rooms, where the GBT functionality can be realized using Commercial Off-The-Shelf (COTS) components. This paper describes efficient physical implementation of the GBT protocol achieved for FPGA devices on Altera and Xilinx devices with source codes developed in Verilog and VHDL. The current platforms are based on Altera StratixIIGX and Xilinx Virtex5. We will start by describing the GBT protocol implementation in detail. We will then focus on practical solutions to make Stratix and Virtex transceivers match the custom encoding scheme chosen for the GBT. Results will be presented on single channel occupancy, resource optimization when using several channels in a chip and bit error rate measurements, with the only aim to demonstrate the ability of both Altera and Xilinx FPGAs to host such a protocol with excellent performances. Finally, information will be given on how to use the available source code and how to integrate GBT functionality into custom FPGA applications. I. GBT PROTOCOL PRESENTATION

Single event upset tests of an 80-Mb/s optical receiver

This paper studies the single event upset (SEU) sensitivity of a radiation-tolerant 80-Mb/s receiver developed for the CMS Tracker digital optical link. Bit error rate (BER) measurements were made while irradiating the receiver with protons and neutrons at different beam energies and incident angles and for a wide range of optical power levels in the link. Monte Carlo simulations have also been used to assist in the interpretation of the experimental results. As expected, the photodiode is the most sensitive element to SEU. The fake signal induced by direct ionization dominates the bit-error cross-section only for protons incident on the photodiode at large angles and low levels of optical power. Comparison of the neutron and proton bit-error cross-sections demonstrates that nuclear interactions contribute significantly to the proton-induced SEU errors and that they will dominate the radiation-induced error rate in the real Tracker application.

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

E-link : A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication

The e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The elink is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable LowVoltage Signaling (SLVS) electrical standard was tested and demonstrated a performance level compatible with our application. Test results are presented. A SLVS transmitter/receiver IP block was designed in 130 nm CMOS technology. A test chip was submitted for fabrication.

The GBTIA, a 5 Gbit/s Radiation-Hard Optical Receiver for the SLHC Upgrades

The GigaBit Transceiver (GBT) is a high-speed optical transmission system currently under development for HEP applications. This system will implement bi-directional optical links to be used in the radiation environment of the Super LHC. The GigaBit Transimpedance Amplifier (GBTIA) is the front-end optical receiver of the GBT chip set. This paper presents the GBTIA, a 5 Gbit/s, fully differential, and highly sensitive optical receiver designed and implemented in a commercial 0.13 µm CMOS process. When connected to a PIN-diode, the GBTIA displays a sensitivity better than uf02d19 dBm for a BER of 10 uf02d12 . The differential output across an external 50 uf057 load remains constant at 400 mVpp even for signals near the sensitivity limit. The chip achieves an overall transimpedance gain of 20 kuf057 with a measured bandwidth of 4 GHz. The total power consumption of the chip is less than 120 mW and the chip die size is 0.75 mm x 1.25 mm. Irradiation testing of the chip shows no performance degradation after a dose rate of 200 Mrad.

Test bench development for the radiation Hard GBTX ASIC

This paper presents the development of the GBTX radiation hard ASIC test bench. Developed for the LHC accelerator upgrade programs, the GBTX implements a bidirectional 4.8 Gb/s link between the radiation hard on-detector custom electronics and the off-detector systems. The test bench was used for functional testing of the GBTX and to evaluate its performance in a radiation environment, by conducting Total Ionizing Dose and Single-Event Upsets tests campaigns.

A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments

The availability of a sub 1-W SerDes for future LHC read-out systems is of paramount importance for building new low-mass inner detectors for HL-LHC. This work reports on the design of two alternative architectures for the serializer block within a high speed transmitter with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Two alternative architectures are implemented using a commercial 65nm LP-CMOS technology. The architectures used are a simple TMR and a code-protected one, and are meant to investigate different strategies to handle SEUs. While using the same technology and flip-flops, the simple TMR architecture results in a consumption of 30 mW, the code-protected one of 19 mW, which are better than 1/4 of the power used in state-of-the-art rad-hard serializers. Early data on robustness to SEU effects are also presented.

A Radiation Tolerant 4.8 Gb/s Serializer for the Giga-Bit Transceiver

This paper describes the design of a full-custom 120:1 data serializer for the GigaBit Transceiver (GBT) which has been under development for the LHC upgrade (SLHC). The circuit operates at 4.8Gb/s and is implemented in a commercial 130 nmCMOS technology. The serializer occupies an area of 0.6 mm and its power consumption is 300 mW . The paper focuses on the techniques used to achieve radiation tolerance and on the simulation method used to estimate the sensitivity to single event transients.