S. Batra

Analysis of ion‐implanted amorphous and polycrystalline silicon films as diffusion sources for ultrashallow junctions

This paper discusses the diffusion of As, P, and B in amorphous and polycrystalline silicon‐on‐single‐crystal silicon systems during rapid thermal annealing and furnace annealing. It is found that the changes of microstructure during annealing play a major role in determining the diffusion profiles in the substrate as well as in the polycrystalline silicon layer. For As or P doping, a drive‐in diffusion results in a much larger grain microstructure for as‐deposited amorphous silicon than for as‐deposited polycrystalline silicon, which leads to the formation of shallower junctions in the substrate for the first case. For B doping, there is little difference in the final microstructure and junction depth between the two cases. At high anneal temperatures, the native interfacial oxide breaks up, causing epitaxial realignment of the polycrystalline silicon film and subsequent enhanced diffusion in the substrate.

Effect of dopant redistribution, segregation, and carrier trapping in As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi/sub 2/ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi/sub 2/. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior. >

Analysis of lateral uniformity of ultrashallow junctions in polycrystalline silicon‐on‐single crystal silicon systems

The lateral uniformity of n+‐p junctions formed by indiffusion of As or P from an amorphous or polycrystalline silicon thin‐film source into the underlying silicon substrate has been investigated using a concentration‐dependent etch and transmission electron microscopy. Grain boundaries act as fast diffusant pipelines and also possibly inject point defects into the substrate, thereby enhancing bulk diffusivities locally in the substrate. Delineated ultrashallow junctions show significant doping lateral inhomogeneities in the substrate for as‐deposited amorphous silicon diffusion sources but not for as‐deposited polycrystalline silicon diffusion sources because of a larger final grain microstructure after annealing in the former case. However, the doping inhomogeneities are gradually smeared out as impurities diffuse deeper into the substrate.

Role of negatively charged vacancies in secondary grain growth in polycrystalline silicon during rapid thermal annealing

It has been reported that there is a drastic increase of grain size in polycrystalline silicon because of secondary grain growth in ultrathin, heavily n‐type doped films upon conventional furnace annealing. There has been very limited work on secondary grain growth during rapid thermal annealing (RTA). This letter presents for the first time extensive data on secondary grain growth in heavily n‐type, P‐doped amorphous silicon‐on‐oxide films during RTA. Grains as large as 16 μm in diameter have been obtained in 160‐nm‐thick films which represent the largest secondary grains and largest grain size to film thickness reported in the literature. The role of charged silicon vacancies is invoked in a new way to explain the observed lower activation energy for grain boundary mobility during secondary grain growth than during normal grain growth.

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted, As-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.

Ultra-shallow junctions in silicon using amorphous and polycrystalline silicon solid diffusion sources

The inter-dependence of diffusion behavior and grain microstructure in amorphous silicon/polysilicon-on-single crystal silicon systems has been studied for rapid thermal and furnace annealing for P and BF2 implants. It is found that the changes of microstructure during annealing play a major role in determining the diffusion profiles in the substrate as well as in the polysilicon layer. For P doping, a drive-in diffusion results in a much larger grain microstructure for as-deposited amorphous silicon than for as-deposited polysilicon, which leads to the formation of shallower junctions in the substrate for the first case. For B doping, there is little difference in the final microstructure and junction depth between the two cases. The P and B junctions formed in the substrate are found to be laterally very uniform in spite of expected doping inhomogeneities due to polysilicon grain boundaries both for as-deposited amorphous silicon diffusion sources and for as-deposited polysilicon diffusion sources.

Boltzmann–Matano analysis based model for boron diffusion from polysilicon into single crystal silicon

The diffusion of boron in single crystal silicon has been modeled following a BF2 or boron implant in a polysilicon layer deposited on a single crystal silicon substrate. The effective concentration‐dependent diffusivities of boron in single crystal have been extracted using Boltzmann–Matano analysis from the experimental boron diffusion profiles measured using secondary ion mass spectrometry. The effective boron diffusivities are found to be independent of the implant dose. A new analytical model for concentration‐dependent boron diffusivities has been implemented in the PEPPER simulation program to accurately model the boron diffusion profiles in single crystal silicon for a polysilicon‐on‐single‐crystal‐silicon structure. The model has been verified for a wide range of furnace anneal conditions (800–950u2009°C, from 30 min to 6 h), and implant conditions (BF2 doses varied from 5×1015 to 2×1016 cm−2 at 70 keV and boron dose of 5×1015 cm−2 at 20 keV).

Effect of grain microstructure on P diffusion in polycrystalline-on-single crystal silicon systems

Grain microstructure has a major impact on diffusion of P in polysilicon-on-single crystal silicon systems both within the polysilicon layer and inside the single crystal silicon substrate. During annealing, P diffuses very rapidly along grain boundaries in the polysilicon layer to the interface, where it undergoes very fast diffusion laterally along the polysilicon-single crystal silicon interface, followed subsequently by slow indiffusion into the underlying substrate. However, the extrapolated Secondary Ion Mass Spectrometry profiles for P reveal a discontinuity at the interface, which is caused by anomalous diffusion behavior similar to the well known “kink” effect observed in single crystal silicon during P diffusion. The high diffusivity tail region is also much less pronounced for polysilicon-on-silicon systems compared to single crystal silicon due to a reduction of interstitial supersaturation in the substrate. This reduction is believed to result from the absorption of interstitials by the grain boundaries which act as sinks for the excess interstitials.

Enhancement of boron diffusion through gate oxides in metal‐oxide‐semiconductor devices under rapid thermal silicidation

It has recently been reported that there is anomalous enhanced diffusion of B through the gate oxide in metal‐oxide‐semiconductor (MOS) structures from B‐implanted, p+‐polycrystalline silicon gates upon annealing in the presence of H or F. This letter discusses the effects of TiSi2 formation on B penetration through the gate oxide in p+ polycrystalline silicon gate MOS devices. From secondary‐ion mass spectrometry analyses, it is found that B penetration effect is enhanced by TiSi2 formation, for 950 and 1100u2009°C rapid thermal annealing, in spite of the fact that the F concentration in the gate oxide for samples with silicide is lower than that for samples without silicide. Furthermore, samples with a one‐step TiSi2 formation process exhibit more serious B penetration effects than those with a two‐step process. This indicates that the effect of silicide on B penetration is more complicated than simply acting as a sink for F. Pileup of B at the silicide/polycrystalline silicon interface, the generation of p...

Anomalous capacitance-voltage behavior due to dopant segregation and carrier trapping in As-implanted polycrystalline silicon and silicided polycrystalline silicon gates

This letter discusses the anomalous capacitance‐voltage characteristics of As‐implanted polycrystalline silicon and amorphous Si gate metal‐oxide‐semiconductor (MOS) structures fabricated with and without a TiSi2 layer. The effects of gate bias and process parameters such as annealing temperature, process details of silicide formation, and polycrystalline silicon grain microstructure on the capacitance‐voltage (C‐V) characteristics have also been studied. It is shown that insufficient As redistribution at 800u2009°C, coupled with carrier trapping at polycrystalline silicon grain boundaries and dopant segregation in TiSi2, causes depletion effects in the polycrystalline silicon gate and in turn, the anomalous C‐V behavior. The depletion tends to increase the ‘‘effective’’ gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥900u2009°C) are sufficient to achieve degenerate doping in the polycrystalline silicon gates and avoid the depletion effects.