S.D. Pinkerton

Observation of single event upsets in analog microcircuits

Selected analog devices were tested for heavy-ion-induced single event upset (SEU). The results of these tests are presented, likely upset mechanisms are discussed, and standards for the characterization of analog upsets are suggested. The OP-15 operational amplifier, which was found to be susceptible to SEU in the laboratory, has also experienced upset in space. Possible strategies for mitigating the occurrence of analog SEUs in space are also discussed. >

Single event upset (SEU) sensitivity dependence of linear integrated circuits (ICs) on bias conditions

The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.

On the suitability of non-hardened high density SRAMs for space applications

Several non-radiation-hardened high-density static RAMs (SRAMs) were tested for susceptibility to single event upset (SEU) and latchup. Test results indicate that at present only a few such device types are suitable for use in space applications. Several additional factors such as susceptibility to multiple-bit upsets and to radiation induced permanent damage need to be taken into consideration before these device types can be recommended. One nonhardened SRAM device type has recently been used on a low-Earth-orbit satellite, enabling the upset rate measured in space to be compared to that predicted from ground-based testing. >

Single-word multiple-bit upsets in static random access devices

Presents the results of an investigation of the SMU (single-word multiple-bit upset) vulnerability of a number of high density SRAM (static random-access memory) device types. The primary objectives of this study were to examine the extent of SMUs in SRAMs, determine design characteristics that predispose devices to this type of upset, and investigate SMU mitigation techniques applicable to space-based electronic systems. The results reported suggest that a nonnegligible SMU rate can be expected for most high-density SRAM types when exposed to the space radiation environment. However, the range of SMU rates is also very large, suggesting that careful selection of device types should be emphasized during the design phase. Furthermore, susceptibility to SEU is not necessarily a reliable indicator of SMU vulnerability. A more important determinant, in many cases, is the architecture of the device, especially the physical separation between logically adjacent cells. It is therefore inappropriate to consider SEU (single event upset) studies to be a proxy for SMU investigations. >

Single ion induced multiple-bit upset in IDT 256K SRAMs

The occurrence of single ion induced multiple-bit upset in IDT71256 256K SRAMs was investigated using high energy heavy ions, with special attention to upsets affecting bits within the same logical memory word.<<ETX>>

SEU and latchup tolerant advanced CMOS technology

Selected microcircuits constructed in National Semiconductors FACT (Fairchild advanced CMOS technology) were tested for heavy-ion-induced single event upset (SEU) and latchup. The devices showed no signs of heavy-ion-induced latchup for linear energy transfer (LET) values up to 120 MeV/(mg/cm/sup 2/). SEU LET thresholds varied within a rather narrow range of 40 to 60 MeV/(mg/cm/sup 2/). The test results suggest that FACT devices will exhibit higher tolerances to the cosmic ray environment than functionally similar microcircuits fabricated in HC/HCT (high-speed CMOS), ALS (advanced low-power Schottky), and LS (low-power Schottky) technologies. >

Bevalac ion beam characterizations for single event phenomena

Linear Energy Transfer (LET) distributions of Bevalac ion beams were measured. Subsequent analysis has called into question the standard assumption of a monoenergetic, single-species beam at Bevalac. Both high LET contaminants in the primary beam and very broad LET peaks in degraded beams were observed. High energy ion beams at other accelerators may possess similar characteristics. The existence of beam impurities may have important ramifications for the interpretation of single-event phenomena observed at high energy accelerator sites.

The impact of ASIC devices on the SEU vulnerability of space-borne computers

Application-specific integrated circuits (ASICs) offer a number of advantages over traditional multicomponent microcircuits, including reductions in both size and power dissipation, and are therefore prime candidates to replace such microcircuits in space borne electronics systems. The results of recent tests of the susceptibilities of various ASIC devices to cosmic ray and trapped proton induced single event upset (SEU) and latchup are reported and are compared to the susceptibilities of the devices that they would replace. This comparison leads to a discussion of the impact of ASIC devices on the SEU susceptibility of spaceborne computers. >

Low dose rate proton irradiation of quartz crystal resonators

Quartz crystal resonators were systematically irradiated with 65 MeV protons to characterize low dose rate radiation-induced degradation. Results indicate: (1) test samples that exhibit large frequency shifts during testing tend to show large frequency shifts prior to irradiation, or during off-irradiation periods; (2) for radiation-sensitive samples, short-term effects seem to decrease after each irradiation on/off cycle (moreover, those devices in which radiation effects do not decrease after a few cycles are not very sensitive); (3) the fabrication process may be an important determinant of susceptibility to low dose radiation-induced degradation; and (4) total-dose effects may be sublinear.

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.