Michael C. Maher

Single event upset (SEU) sensitivity dependence of linear integrated circuits (ICs) on bias conditions

The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.

Impact of passivation layers on enhanced low-dose-rate sensitivity and pre-irradiation elevated-temperature stress effects in bipolar linear ICs

Final chip passivation layers are shown to have a major impact on the total dose hardness of bipolar linear technologies. It is found that devices fabricated without passivation layers do not exhibit enhanced low-dose-rate sensitivity (ELDRS) or pre-irradiation elevated-temperature stress (PETS) sensitivity, whereas devices from the same production lot fabricated with either oxide/nitride or doped-glass passivation layers are ELDRS and PETS sensitive. In addition, removing the passivation layers after fabrication can mitigate ELDRS and PETS effects. ELDRS and PETS effects do not appear to be inherently related to circuit design or layout, but are related to mechanical stress effects, hydrogen in the device, or a combination of the two. These results suggest that proper engineering of the final chip passivation layer might eliminate ELDRS and PETS effects in bipolar integrated circuits.

Annealing behavior of linear bipolar devices with enhanced low-dose-rate sensitivity

The post-irradiation annealing behavior of total dose degradation in LM139 comparators fabricated in National Semiconductor Corporations (NSC) enhanced low-dose-rate sensitive (ELDRS) linear bipolar technology is examined. Data show that a large fraction of the radiation-induced increase in input bias current recovers after a 100/spl deg/C anneal. The recovery in input bias current is linked to a significant amount of interface-trap annealing at 100/spl deg/C. This is qualitatively consistent with previous data on interface-trap annealing and recent models for interface-trap annealing associated with hydrogen motion at the silicon/silcon dioxide interface. The annealing results have implications for hardness assurance testing. If the radiation induced charge that is responsible for ELDRS (whether it be interface or border traps) can anneal at 100/spl deg/C, these data suggest that elevated temperature irradiations sometimes used to bound the ELDRS response of ICs may also cause some annealing of radiation-induced charge. These data help explain why high-dose-rate irradiations at elevated temperatures in some cases underestimate low-dose-rate degradation. In addition, these data confirm that high-dose-rate irradiations followed by elevated temperature anneals do not mimic the mechanisms that cause enhanced degradation at low dose rates in devices with ELDRS.

Laser-induced and heavy ion-induced single-event transient (SET) sensitivity measurements on 139-type comparators

We have measured the single-event transient (SET) response for a number of 139-type comparators with differing topologies. In this paper, we present the results from pulsed laser measurements on a number of different 139-type devices, as well as heavy ion measurements on a new RM139 device from NSC. Devices tested with the laser included the HS-139RH, PM139, LM139 and a more recent version of LM139 from NSC. We discuss the effects of different device topologies on SET sensitivity. Our results agree qualitatively with SPICE model calculations of LM139s by Johnston et al.

Origins of total-dose response variability in linear bipolar microcircuits

LM111 voltage comparators exhibit a wide range of total-dose-induced degradation. Simulations show this variability may be a natural consequence of the low base doping of the substrate PNP (SPNP) input transistors. Low base doping increases the SPNPs collector to base breakdown voltage, current gain, and sensitivity to small fluctuations in the radiation-induced oxide defect densities. The build-up of oxide trapped charge (N/sub OT/) and interface traps (N/sub IT/) is shown to be a function of pre-irradiation bakes. Experimental data indicate that, despite its structural similarities to the LM111, irradiated input transistors of the LM124 operational amplifier do not exhibit the same sensitivity to variations in pre-irradiation thermal cycles. Further disparities in LM111 and LM124 responses may result from a difference in the oxide defect build-up in the two part types. Variations in processing, packaging, and circuit effects are suggested as potential explanations.

Passivation layers for reduced total dose effects and ELDRS in linear bipolar devices

It is shown that final chip passivation layers can have a significant impact on total dose hardness. A number of final chip passivation layers are evaluated to identify films that mitigate enhanced low-dose-rate sensitivity (ELDRS) in National Semiconductor Corporations linear bipolar technologies. It is shown that devices fabricated with either a low temperature oxide or a tetraethyl ortho silicate passivation do not exhibit significant ELDRS effects up to 100 krad(SiO/sub 2/). Passivation studies on CMOS SRAMs suggest that it is unlikely that the passivation layers (or processing tools) are acting as a new source of hydrogen, which could drift or diffuse into the oxide and increase ELDRS sensitivity. Instead, it is possible that the passivation layers affect the mechanical stress in the oxide, which may affect oxide trap properties and possibly the release and mobility of hydrogen. Correlations between mechanical stress induced by the passivation layers and radiation degradation are discussed.

Hardness assurance implications of bimodal total dose response in a bipolar linear voltage comparator

The total dose response of transistors and circuits from a single wafer lot has been measured for high and low dose rate and elevated temperature irradiations. A bimodal irradiation response is observed in the circuit response that is shown to be a result of the input transistors. Hardness assurance sampling plans are examined for their adequacy to deal with the bimodal response distributions.

SEU and latchup tolerant advanced CMOS technology

Selected microcircuits constructed in National Semiconductors FACT (Fairchild advanced CMOS technology) were tested for heavy-ion-induced single event upset (SEU) and latchup. The devices showed no signs of heavy-ion-induced latchup for linear energy transfer (LET) values up to 120 MeV/(mg/cm/sup 2/). SEU LET thresholds varied within a rather narrow range of 40 to 60 MeV/(mg/cm/sup 2/). The test results suggest that FACT devices will exhibit higher tolerances to the cosmic ray environment than functionally similar microcircuits fabricated in HC/HCT (high-speed CMOS), ALS (advanced low-power Schottky), and LS (low-power Schottky) technologies. >

Elimination of Enhanced Low-Dose-Rate Sensitivity in Linear Bipolar Devices Using Silicon-Carbide Passivation

The type of final chip passivation layer used to fabricate linear bipolar circuits can have a major impact on the total dose hardness of some circuits. It is demonstrated that National Semiconductor Corporation linear bipolar devices fabricated with only an amorphous silicon carbide passivation layer do not exhibit enhanced low-dose-rate sensitivity (ELDRS), while devices from the same production lot fabricated with other types of passivation layers are ELDRS sensitive. SiC passivation possesses mechanical, electrical and chemical properties that make it compatible with linear device fabrication processes. These properties of SiC passivation layers, combined with the excellent radiation response of devices passivated with SiC, make SiC passivation layers a very attractive choice for devices packaged in either ceramic or plastic-encapsulated packages for use in space environments

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.