S. Intekhab Amin

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ~ 0.56 mA/μm), ION/IOFF ratio ~ 9.12 × 1013 and an average subthreshold swing (AV-SS ~ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Performance investigation of charge plasma based dual material gate junctionless transistor

In this paper, the design aspects of charge plasma based junctionless transistors viz., (1) doping-less dual material double gate (DL-DMDG) junctionless transistor and (2) Gate stacked architecture of DL-DMDG JLT are used to evaluate the device performances. The n+ source/drain regions are formed by employing charge plasma technique over the intrinsic silicon. Dual material gate architecture helps to minimize the delay and gate stacked architecture helps to have better control over channel region. The performances metrics such as, subthreshold slope (SS), fluctuation in threshold voltage (VT), drain induced barrier lowering (DIBL), intrinsic delay and energy delay product are analysed for different silicon film thickness (Tsi), gate length (LG), and gate work-functions difference (δW). The comparative analysis has been done with conventional heavily doped dual material double gate (DMDG) JLT and its gate stacked architecture (GSDMDG) of JLT. The SS, VT, intrinsic delay and energy delay product of DL-DMDG and DL-GSDMDG JLTs are less sensitive to the variations in aforementioned device parameters as compared to conventional doped DMDG and GSDMDG JLTs. Moreover, DL-GSDMDG JLT shows remarkable improvement over other mentioned device configurations.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high- k gate dielectric material that could replace SiO 2 . We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k -values on the tunneling current of the DGJLT.