Naushad Alam

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half-select issue, ION/IOFF ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02× greater area as compared with 6T SRAM cells. However, 6.9× higher ION/IOFF ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.

Carbon nanotube interconnects for low-power high-speed applications

This paper investigates the prospects of mixed bundle of Carbon Nanotubes (CNT) as low-power high-speed interconnects for future VLSI applications. The power dissipation and delay of CNT bundle interconnects are examined and compared with that of the Cu interconnects at the 32-nm technology node. We evaluated and compared various performance metrics of interconnects with both CMOS and Carbon Nanotube Field Effect Transistor (CNFET) driver and FO4 load using transmission line model. The results show that CNT bundle consumes 1.5 to 4 folds smaller power than Cu for intermediate and global interconnects. The CNT bundle interconnects are also faster than Cu except for local interconnects. It is concluded that the mixed bundle of CNTs is a promising candidate for intermediate and global interconnects in future technologies.

Analysis of carbon nanotube interconnects and their comparison with Cu interconnects

The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects in very deep submicron (VDSM) technology. This paper presents a comprehensive analysis of mixed bundles of CNTs and compares various transmission line model interconnect parameters (R, L, & C) with that of the Cu interconnects at 32nm technology node. Results show that the mixed bundles of CNTs have smaller value of R & C for Intermediate and Global level interconnects. However, for Local interconnects Cu wire has smaller value of R and the value of C is comparable to that of the bundle of CNTs.

Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance

This paper investigates the circuit performance improvement through poly-pitch scaling in strain engineered devices. We use tensile contact etch stop liner(t-CESL), compressive contact etch stop liner(c-CESL), embedded SiC and SiGe as stress sources in NMOS and PMOS devices. It is observed that poly-pitch optimization delivers ~18% and ~13% reduction in delay of an inverter driving FO4 and FOl loads respectively. We observe that, in the presence of process induced mechanical stress; the optimum poly-pitch depends upon the size of the driver and the load. Finally, we present a model for choosing optimum poly-pitch for enhanced circuit performance while taking care of the power constraint.

Gate-Pitch Optimization for Circuit Design Using Strain-Engineered Multifinger Gate Structures

Optimal transistor sizing and layout using multifinger gate structures (MFGSs) in mechanical stress-engineered CMOS technology is a major issue. We observe that the pull-down and pull-up delay of an inverter using seven-fingered devices with fan-out-of-four (FO4) load increases by ~ 9% and ~ 14%, respectively, compared with the FO4 delay of a reference inverter using single-finger gate structure. On the other hand, doubling gate-pitch in the above inverter improves the pull-down and pull-up delay by ~ 18% and ~ 23%, respectively, compared with the delay of the reference inverter. In this brief, we present a methodology of transistor sizing and layout optimization for MFGSs in stress-engineered CMOS circuits. For this, we derive and validate a modified model of logical effort (LE), where LE is expressed as a function of the number of fingers (NF) and gate-pitch (Lpp). Using our model, we reduce the error in the estimated delay of a four-stage buffer with FO4 from ~ 9% to ~ 1%. Using our methodology, we improve the circuit performance by 7%.

An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design

Strain engineering for performance enhancement is an integral part of a state-of-the-art CMOS process flow. However, use of stressors makes the performance of CMOS devices layout dependent. Performance variability arising due to the use of stressor materials is often referred to as Layout Dependent Effect (LDE) variability. The existing delay models do not take LDE into consideration and, therefore, results into unaccounted change in performance and degraded design robustness. In this paper we propose an analytical delay model for Inverter, 2-input NAND and NOR gates while considering LDE variability due to the use of strain engineered devices. We compare our derived model with TCAD calibrated HSPICE simulation results and observe that our model estimates delay well for varying transistor sizes, load capacitances and input signal transition times.

Performance comparison and variability analysis of CNT bundle and Cu interconnects

Bundles of carbon nanotubes (CNT) have potential to replace on-chip copper (Cu) interconnects due to their large conductivity and current carrying capabilities. Analysis of the impact of process variations on CNT bundles relative to standard copper interconnects is important for predicting the reliability of CNT based interconnects. This paper investigates the impact of process variations on the resistance and capacitance of CNT bundle and compare it with the Cu interconnects at the 32nm technology node (year 2013). HSPICE simulation results show that CNT bundle consumes 1.5 to 2 folds smaller power and are 1.4 to 3 times faster than Cu for Intermediate and Global interconnects. However, for local interconnect Cu wire outperforms the CNT bundle. It was observed that process variation has comparable effects for CNT bundle and Cu wire except for Local interconnects.

Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory

This paper presents a low leakage, half-select free SB9T SRAM cell with good static and dynamic read/write performance along with smaller area. The proposed cell offers high Read SNM and low leakage power among the cells considered in this work while causing an area overhead of only 37% of that of 6T cell. Simulation results show that the proposed cell offers 4.2x higher RSNM, 33% lower mean leakage power as compared to 6T SRAM. The proposed cell also offers more than 10x higher Ion/Ioff ratio that holds potential to compensate for the area overhead by having more number of cells connected to the same bitline. The proposed cell has longer write delay because of the single bitline structure; however, it offers lower read delay and smaller read/write power to that of the 6T cell. Monte Carlo simulations using HSPICE at 16nm technology were performed by incorporating local and global variations and it is observed that the proposed cell offers high robustness against process variations. Therefore, the proposed cell could be a good choice for applications that demand high stability, low power, low area and moderate speed.

The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices

Abstract In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors.

Subthreshold deep submicron performance investigation of CMOS and DTCMOS biasing schemes for reconfigurable computing

This paper investigates subthreshold CMOS logic for ultra low power applications on next generation reconfigurable devices. The performance characteristics of key digital building blocks such as arithmetic units, multiplexers and look-up-tables have been analyzed in terms of speed, power dissipation and power delay product using Berkeley Predictive Technology models at 22nm technology node for both the conventional subthreshold CMOS (CMOS) and the dynamic threshold subthreshold CMOS (DTCMOS). Simulation results show that DTCMOS has lower PDP and sensitivities to process variations compared to CMOS for the digital blocks. Moreover, the PDP of blocks can be further improved by using longer channel lengths.