S. Jaganathan
University of California, Santa Barbara
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Publication
Featured researches published by S. Jaganathan.
radio frequency integrated circuits symposium | 1999
Q. Lee; D. Mensa; J. Guthrie; S. Jaganathan; T. Mathew; Y. Betser; S. Krishnan; S. Ceran; Mark J. W. Rodwell
We report a 66 GHz emitter coupled logic (ECL) 2:1 static frequency divider using InAlAs/InGaAs transferred-substrate HBTs. To our knowledge this is the fastest static divider reported in any semiconductor technology.
international conference on indium phosphide and related materials | 2000
J. Guthrie; Miguel Urteaga; D. Scott; D. Mensa; T. Mathew; Q. Lee; S. Krishnan; S. Jaganathan; Y. Betser; Mark J. W. Rodwell
We report W band MMIC power amplifiers in an InGaAs/InAlAs HBT technology. A cascode amplifier with an emitter area of 100 /spl mu/m/sup 2/ and a total die size of 0.42/spl times/0.36 /spl mu/m/sup 2/ delivers 10 dBm at 75 GHz under 1.7 dB of gain compression. A balanced amplifier composed of two such cascode cells delivers 10.7 dBm at 78 GHz under 1 dB of gain compression. A common-base amplifier delivers 9.7 dBm at 82.5 GHz under 0.8 dB of gain compression. To the best of our knowledge, these results represent the best reported power performance at W band for HBT MMIC amplifiers.
ieee gallium arsenide integrated circuit symposium | 2000
S. Jaganathan; D. Mensa; T. Mathew; Y. Betser; S. Krishnan; Y. Wei; D. Scott; Miguel Urteaga; Mark J. W. Rodwell
We report an 18 GHz clock-rate, 2/sup nd/ order continuous-time /spl Sigma/-/spl Delta/ modulator implemented using InP transferred substrate HBTs. Under two-tone test conditions, the modulator achieved 43 dB and 33 dB SNR at signal frequencies of 500 MHz and 990 MHz, respectively. The latter is equivalent in performance to a 1.98 GS/s Nyquist-rate ADC with 6.2 bits resolution. The IC occupied 1.95 mm/sup 2/ die area and dissipated /spl sim/1.5 W.
international conference on indium phosphide and related materials | 1999
J. Guthrie; D. Mensa; T. Mathew; Q. Lee; S. Krishnan; S. Jaganathan; S. Ceran; Y. Betser; Mark J. W. Rodwell
We report HBT integrated circuits fabricated by substrate transfer on 50 mm diameter copper/polymer substrates. Layout and packaging of complex /spl sim/100 GHz circuits is facilitated by the microstrip wiring environment and the low ground lead inductance it affords. For ICs operating above 100 GHz, the process allows radical scaling of the microstrip dielectric thickness without requiring handling of delicate thinned III-V wafers. The process can provide greatly improved heatsinking. Furthermore, full 50 mm wafers can be processed incorporating transferred substrate HBTs, devices which have obtained >500 GHz f/sub max/.
Electronics Letters | 1999
D. Mensa; Q. Lee; J. Guthrie; S. Jaganathan; Mark J. W. Rodwell
Electronics Letters | 2001
T. Mathew; H.J. Kim; D. Scott; S. Jaganathan; S. Krishnan; Y. Wei; Miguel Urteaga; Stephen I. Long; Mark J. W. Rodwell
Solid-state Electronics | 1999
Mark J. W. Rodwell; Q. Lee; D. Mensa; J. Guthrie; S.C. Martin; R.P Smith; R. Pullela; B. Agarwal; S. Jaganathan; T. Mathew; Stephen I. Long
Electronics Letters | 2000
S. Krishnan; D. Mensa; J. Guthrie; S. Jaganathan; T. Mathew; R. Girish; Y. Wei; Mark J. W. Rodwell
Electronics Letters | 2001
T. Mathew; S. Jaganathan; D. Scott; S. Krishnan; Y. Wei; Miguel Urteaga; Mark J. W. Rodwell; Stephen I. Long
Archive | 2001
Y. Betser; D. Scott; D. Mensa; S. Jaganathan; T. Mathew; Mark J. W. Rodwell
