S. Jan

New Wideband Miniature Branchline Coupler on IPD Technology for Beamforming Applications

In this paper, we present a new wideband miniature branchline coupler as a key circuit to be integrated in 60-GHz packaged beamforming networks for phased-array antennas. First, the integrated passive device (IPD) technology from STMicroelectronics is investigated in the mm-wave range through the simulation, fabrication, and measurements of a microstrip line and a simple hybrid coupler. Then, a novel coupler topology with emphasis on miniaturization and broadband operation is theorized. Analytical equations are derived and a 60-GHz coupler is optimized on IPD technology. Measurement results are discussed and compared with state-of-the art publications. The whole 57-66-GHz bandwidth is efficiently covered with the three following performance: -10-dB impedance matching, ±1-dB amplitude imbalance, and ±5° phase imbalance. As an application example, the novel coupler is integrated into a 4 × 4 Butler matrix suitable for an array-antenna demonstrating stateof-the art performance in terms of insertion loss and phase error. The measurement of different samples shows low variation of the IPD process because of very good reproducibility making it a suitable candidate for circuits operating in the 60-GHz band.

Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

Millimeter-wave characterization of Si/SiGe HBTs noise parameters featuring f T /f MAX of 310/400 GHz

High frequency noise parameters (NFmin, Rn, Bopt and Gopt) determination of Si/SiGe HBTs from STMicroelectronics B5T technology are provided for the first time in the millimeter-wave range. In this paper, an integrated tuner is used for the extraction of high frequencies noise parameters with the multi-impedance method. The designed tuner is composed an active part with a low noise amplifier (LNA) and a passive part with a high performances travelling wave digitally tunable capacitance (DTC), both in series with a transmission line design for phase shifting. Measurements exhibit a state of the art NFmin lower than 2 dB at 68 GHz for the HBT.

4-Port isolated MOS modeling and extraction for mmW applications

This paper reports on the extraction of the small-signal equivalent circuit of 28nm isolated RF MOS transistors using on-wafer 4-port S-parameter measurements up to 50GHz. It shows that modeling accuracy of RF MOS is significantly enhanced via a 4-resistance cross-type substrate network plus an isolation sub-network. In addition, the impact of substrate network on Mason gain is presented. Finally, the whole methodology is shown to be very promising to extract and model RF MOS in sub-threshold region for low power/high frequency applications.

Integration of cellular front end modules on advanced high resistivity SOI RF CMOS technology

Since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning front end module (FEM) integration on silicon [1]. In this quest, SOI technology has emerged as the technology of choice [2] since the antenna switch and the power amplifier (PA) have been successfully integrated on SOI [3, 4]. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.

A high quality factor varactor technology evaluation

Providing a high quality factor scalable varactor in an integrated technology is a wager. How to insure that your device will give the highest quality factor possible? In order to response this questions, we let the bases of a varactor gauge combining electrical performance and geometrical sizes. Giving a targeted capacitance, it could furnish a qualitive idea of the adequacy with technology performance. It could furnish also a indicator for comparison with other devices. As example of varactor gauge application, we present a comparison between two diode varactor devices in two BiCMOS technologies.