S. Kayano

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands the scale of a neural network by interconnecting multiple chips without reducing performance, is described. The chip integrates 336 neurons and 28224 synapses with a 1.0- mu m double-poly-Si double-metal CMOS technology. The operation speed is higher than 1*10/sup 12/ connections per second per chip. It is estimated that the network scale can be expanded to several hundred chips. In the case of 200-chip interconnections, the network will consist of 3360 neurons and 5,644,800 synapses. >

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

THE MEMORY CAPACITY OF SRAMs have quadrupled over the past three years. In ’87, several 1Mb SRAMs whose access times were more than 25ns have been r e p ~ r t e d ~ ” ’ ~ ’ ~ . However, access time below 25ns is necessary, expecially for high-performance computer systems. Fast SRAMs, usually organized in x 1 or x 4, are fabricated by exchanging the A1 layer mask5. But, high-density SRAMs face extended testing time, as in DRAMs. This report will describe a 1Mb CMOS SRAM with a 14ns access time and a variable bit-organization function, whereby a lMbx1 RAM can be changed to 256Kx4, t o reduce testing time. To shorten the access time we need a fast word line selection, a highly sensitive sense amplifier, rapid data transfer from a sense amplifier t o a data output buffer, and a small delay time in the data output buffer. To minimize word line selection time, a small word line CR-delay, high speed decoding-and powerful word line driver are indispensable. Figure 1 shows a block diagram of the RAM, where the 1Mb memory cell array consists of 512 rows and 2048 columns, which is divided into 32 blocks. Each block includes 512 rows and 6 4 columns with one redundant column. The word line is formed by the polycide with a sheet resistance of 5s2 /square. This short and low-resistivity word line structure reduces the word line delay time to 0.5ns. Address signals are split into four groups (X, Y, Z and W). The X-, Y-, Zand Waddress signals are uscd for the selection of row, column, block and sense amplifier, respectively. The W-address is used only in l M b x l organization. Figure 2 shows the word-line selection circuit. The divided word line architecture is adopted6. The block row decoder is composed of a NAND-gate and a CMOS inverter. This two-stage decoder gives an expanded word-line drivability.

A high-density data-path generator with stretchable cells

This paper describes a newly developed module generator for cell-based design which generates a data-path layout comparable to a handcrafted one both in speed and in transistor density. The chip designer enters his schematic data-path diagram using the configurable function block library provided. There is no constraint either in the number of function blocks used, or in how to interconnect them. The data-path generator generates the function blocks, which are components of the data-path, and automatically places and routes them. The configurable function blocks were developed in 0.8-/spl mu/m double metal CMOS technology. A new cell structure suitable for over the cell routing, called stretchable cell with access free terminals, is adopted as a bit-slice element of the data-path generator. This removes the routing region outside the cell for the wiring between function blocks, and a high density layout can be obtained. Also because of the new cell structure, there is no upper limit on the number of tracks per bit. Using this data-path generator, several data-paths were generated with high density of more than 6k Trs./mm/sup 2/. >

A soft error improved 7 ns/2.1-W GaAs 16-kb SRAM

A GaAs 4 K*4 b SRAM (static RAM) with improved alpha particle immunity is presented. By using a novel circuit technology and a buried p-layer FET, the critical charge of the memory cell has been increased and the collected charge decreased. The soft error rate of a 16-kb SRAM is reduced by about four orders of magnitude compared to that of a GaAs 4-kb SRAM consisting of conventional memory cells; it is also less than that of the commercially available silicon 1-kb ECL RAM. An address access time of 7.0 ns with 2.1-W power dissipation has been obtained at 75 degrees C. The RAM operates at the single supply voltage of 1.8 V.<<ETX>>

Improvement of soft-error rate in MOS SRAMs

Two techniques which reduce the alpha -particle-induced soft-error rate (SER) in MOS static RAMs (SRAMs) are described. The mechanism of the soft error is the high-resistive load memory cell is analyzed. It is found that the dependence of SER on the cycle time is caused by the potential drop in the high storage node, which is produced by the threshold current through the driver and access transistors in the memory cell. Improvement methods to suppress the subthreshold current are presented. One method utilizes high-threshold-voltage transistors in the memory cell. The other sets the selected word-line level lower than the supply voltage. Using these methods, the high storage node potential is kept at the supply voltage in spite of the small conductance of the load resistor. The effect is confirmed in 256 kbit CMOS SRAMs. The dependence of SER on the cycle time becomes negligible, and SER is improved by two orders of magnitude. >

A GaAs 16 K SRAM with a single 1-V supply

A GaAs 4 K/spl times/4-b static random access memory (SRAM) with 11-ns access time and 1-W power dissipation is described. The device is fabricated using 1.0-/spl mu/m WSi/SUB x/ selfaligned gate metal semiconductor FET (MESFET) and double-level interconnection technology. Optimization of fan-out and adoption of an address precoder circuit enable both fast access time and low power dissipation. The SRAM operates with a single 1.0-V supply.

A 5-ns GaAs 16-kb SRAM

A GaAs 4 K*4-b static-Ram (SRAM) with high speed and high reliability has been developed for practical systems. By adopting a novel basic circuit technique to the peripheral circuits, the RAM operates over a wide temperature range. By using a novel memory cell, the soft-error rate is reduced to less than that of commercial silicon emitter-coupled-logic (ECL) RAMs. Furthermore, by adopting a triple-level interconnection process, the chip area is reduced to 58% of that using a double-level one. The RAM operates at a single supply voltage of 1.8 V. At an ambient temperature of between 25 and 100 degrees C, the RAM is guaranteed a 5.0-ns access time, 2.0-W power dissipation, and +or-0.1-V supply voltage tolerance. >

A macro analysis of soft errors in static RAMs

In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming alpha -particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-k Omega resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs. >

A double-word-line structure in bipolar ECL random access memory

A double-word-line structure to improve the soft error rate in a bipolar ECL RAM that has resistor-loaded and Schottky-barrier-diode (SBD) clamped memory cells is proposed. The resistor in the memory cell is connected to the first word line and the SBD to the second one, whereas both are connected to one word line in the conventional structure. The potential drop between the two word lines causes shifts of SBD clamp potential in unselected cells, and results in large potential difference in the data storage-node pairs and high soft-error immunity. The soft-error rate of the 4-kb RAM with the double-word-line structure is decreased to 1/100 of that of the conventional one, retaining an access time of 5.5 ns and minimum write-pulse width of 2.4 ns. The improvement does not accompany any degradation in electrical characteristics such as access time and write-pulse width.

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing

A reduced word-line voltage swing (RWS) circuit configuration that results in a high-speed bipolar ECL (emitter coupled logic) RAM is proposed. The write operation can be performed with the configuration in the condition of reduced word-line voltage swing, which causes write operation error in conventional circuit configurations. The proposed configuration cuts off the hold current of the selected memory cell, and then the low-voltage node is charged up through the load p-n-p transistor. A 16-kb ECL RAM with a p-n-p loaded memory cell was fabricated by advanced silicide-base transistor (ASBT) process technology. A 2-ns access time was obtained with 1.8-W power consumption in which the word-line voltage swing was reduced by 0.7 V from a conventional case. Simulation results show that the access time is improved by 25% compared with a conventional case. Simulation results also show that writing time becomes comparable with the conventional time of 1.7 ns when the load p-n-p transistor has a saturation current of 5.0* 10/sup 17/ A and a current gain of 1.0. The saturation current is 5 times larger and the current gain is 5 times smaller than those of the standard lateral p-n-p transistor. >