Yasunobu Nakase

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface

SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.

A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture

A new redundant binary (RB) architecture for a high-speed multiplier is presented. In this architecture, a pair of partial products is converted to one RB number by inverting one of the pair without additional circuitry or latency. Generated RB partial products are added by the Wallace tree of improved RB adders (RBAs) which have a latency of 0.9 ns, and converted to a normal binary (NB) number by a simply structured RB-to-NB converter in which the carry-propagation circuit is constructed only with simple selector circuits. A 54/spl times/54-bit multiplier is designed using 0.5-/spl mu/m CMOS technology. A multiplication time of 8.8 ns is obtained by SPICE2 simulation for a supply voltage of 3.3 V which is the fastest that has been reported for 54/spl times/54-bit multipliers.<<ETX>>

A 64 bit carry look-ahead CMOS adder using Modified Carry Select

We present a 64 b Carry Look-ahead (CLA) adder having a 2.6 ns delay time at 3.3 V power supply within 0.27 mm/sup 2/ using a 0.5 /spl mu/m CMOS technology. We derived its structure from considering the tradeoffs between speed and area. This consideration includes not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. Moreover we introduced a new carry select scheme called Modified Carry Select (MCS). MCS has 20% area advantage over the conventional Carry Select Adder (CSA).

0.5 V Start-Up 87% Efficiency 0.75 mm² On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

An on-chip low power single-inductor dual-output (SIDO) DC-DC boost converter is proposed for battery and solar cell operating sensor network applications. A proposed feed forward control determines the Ton/Toff ratio precisely for each output without any compensation or linear capacitor. This feature helps reduce the costs of the external components and utilize an inexpensive process technology. A test chip was fabricated by 190-nm flash-memory embedded micro-computers CMOS process technology and can achieve an efficiency of 87% with a small area size of just 0.75 mm2. For solar cell operation, a 0.5 V start-up was achieved even with a high threshold voltage of 0.7 V with a proposed forward back biased charge pump. A constant voltage algorithm was implemented as a maximum power point tracking (MPPT) control. With this MPPT control, a solar cell with an open voltage of 1.03 V and a short current of 83 mA was able to charge a super capacitor of 0.4 F up to 5 V within 80 s.

Leading-zero anticipatory logic for high-speed floating point addition

This paper describes new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significand. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with 1.8% penalty in transistor count. The FADD core using the proposed logic operates at 160 MHz, where the core has been fabricated with 0.5 /spl mu/m CMOS technology with triple metal interconnections.

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]

For original article see H. Suzuki, H. Morinaka, H. Makino, Y. Nakase, K. Mashiko and T. Sumi, ibid., vol.31, pp.1157-69 (Aug. 1996). I have read with a great interest the article by H. Suzuki et al. I am familiar with their work, and I found their approach interesting. The idea used to simplify the leading zero anticipator (LZA) I found innovative and an improvement over the one used in the IBM RS/6000. However, I found the LZ counter circuit shown in the paper similar to the LZ counter circuit that I have published previously in the period from 1992-94.

A 300 MHz dual port graphics RAM using port swap architecture

Graphics controllers are required to implement more functions such as 3D-RAM control and NTSC encoder. The color palette SRAM has been a great area eater in the controllers because of its dual port organization. Its memory cell size has been more than 50% larger than those of single port SRAMs. Single bit-line read/write architectures are effective for area reduction. However, there are problems of operation reliability or slow speed. The port swap architecture realizes a small memory cell size without the problems. The cell size is reduced more than 24%. The color palette with this architecture is fabricated in a 0.5 /spl mu/m CMOS process technology and operates up to 300 MHz. This speed is enough to support the practical highest resolution monitors in the world.

A 286 MHz 64-bit floating point multiplier with enhanced CG operation

High speed floating point (FP) multipliers are essential for high speed calculation systems because increasingly large numbers of FP multiplications must be carried out in various applications such as scientific calculation and computer graphics (CG). CG, in particular, requires enormous amount of FP multiplications to obtain high quality images required for multimedia systems. To realize high speed, the critical path delay must be minimized. In this paper, we discuss a method to shorten the delay time of the critical path. Then we present an FP multiplier design based on the method. A special function for CG is also implemented without increasing the critical path delay. Finally, we show the fabrication and test results of the FP multiplier.

A macro analysis of soft errors in static RAMs

In the soft error phenomenon in static RAMs (SRAMs), the mechanism of data upset is more complicated than in dynamic RAMs (DRAMs) because the storage nodes in the memory cells are connected to the power supply via load element. Therefore the critical charge has been evaluated only by computer simulation. The charge which is supplied via load element is estimated analytically, assuming alpha -particle-induced current being constant. The charge which is fed through the load element contributes to the increase of the critical charge in a 1-kbit emitter-coupled logic (ECL) RAM with a 10-k Omega resistor load. In ECL RAMs or MOS SRAMs with a larger resistor, the contribution of the charge which is fed through the load element is hardly expected, and the critical change in such RAMs is evaluated by the stored charge like DRAMs. >