Kenji Anami

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

This paper describes a divided word-line (DWL) structure which solves inherent problems encountered in VLSI static RAMs. The key feature is to divide the word-line and to select it hierarchically with little area penalty using conventional process technology. In the application of the DWL structure, an 8K /spl times/ 8 full CMOS RAM has been developed with 2-/spl mu/m double polysilicon technology. The RAM has a typical access time of 60 ns. An operating current of 20 mA was obtained with a simple static design. The six-transistor cell configuration achieved a low standby current of less than 10 nA. For further improvement in speed, the second poly-Si layer was replaced with a polycide (poly-Si + MoSi/SUB 2/) layer, thus providing a 50-ns address access time.

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

Design consideration of a static memory cell

Describes design criteria for high-density low-power static RAM cells with a four-transistor two-resistor configuration. The states of the cell latch are expressed by a DC stability factor introduced from transfer curves of the inverters in the cell. The criteria use only static conditions for read/write/retain operations. The designed cell, considering mask-misalignment, measured 22.8/spl times/27.6 /spl mu/m with 2.5 /spl mu/m layout rules. From the evaluation of dynamic characteristics, it was shown that the 16K RAM using the cell had a sufficient operating margin.

A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond

This paper describes a distributed globally replaceable redundancy (DGR) scheme which achieves a higher optimization of the trade-off between yield enhancement and chip area penalty. A newly developed yield simulator using the Monte Carlo method has estimated the effectiveness of the DGR scheme in a quantitative manner. The new redundancy scheme is expected to enhance the yield by several times compared with conventional redundancy in the early stages of production. The DGR scheme has been successfully implemented in an experimental 4 Mb SRAM with a 3.0% area overhead and an average redundancy usage efficiency of 61% has been obtained in repaired pass chips.

SOFT ERROR ANALYSIS OF FULLY STATIC MOS RAM.

The static MOS RAM with the polysilicon resistive load for the cell has been analyzed with respect to alpha-particle induced soft error phenomena. The analytical model of soft error will be presented and the effective critical charge Qcrit will be derived. Fully static 16 K-bit NMOS RAMs were fabricated as test vehicles, which were exposed to Am-241 radiation sources for an accelerated test method. The error rate depends on the cycle time and the cell pull-up resistance in the shorter cycle time operation. But in the longer cycle mode, it is regardless of them. Some techniques for error rate reduction which involve thinning gate oxide thickness, adopting Hi–C structure and cell layout techniques will be introduced and their effects will be discussed.

A 920 gate DSA MOS masterslice

A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.

A 920 gate masterslice

An MOS masterslice chip with up to 920 gates, 3W dissipation and 3ns/gate propagation delay time for random logic LSIs will be reported.

An asymmetric memory cell using a C-TFT for single-bit-line SRAM's

This paper proposes a compact single-bit line SRAM memory cell, which we call an asymmetric memory cell (AMC), using a complementary thin-film transistor (C-TFT). A C-TFT is composed of a top-gate n-channel TFT and a bottom-gate p-channel TFT. The proposed cell size can be reduced to 88% as compared with the conventional one using 0.4-/spl mu/m design rules. Stable read and write operations under low-voltage can be realized by using a C-TFT.

A fast 8K × 8 mixed CMOS static RAM

This paper describes a fast 8K × 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2-µm design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 µm2and design of the die in 34.3 mm2.