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Dive into the research topics where S. Kumashiro is active.

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Featured researches published by S. Kumashiro.


international conference on simulation of semiconductor processes and devices | 2000

HiSIM: a drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction

Masami Suetake; K. Suematsu; H. Nagakura; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; S. Kumashiro; Tetsuya Yamaguchi; S. Odanaka; Noriaki Nakayama

We present here the MOSFET model HiSIM (Hiroshima University Starc IGFET model). As HiSIM employs the drift-diffusion approximation and preserves correct modeling of the surface potential in the channel, it is not only accurate, but additionally, model parameter number is small, parameter interdependence is removed, and parameter extraction becomes easy. Measured current-voltage characteristics of advanced MOSFETs are thus reproduced with only 19 model parameters.


IEEE Transactions on Electron Devices | 2001

Physical modeling of the reverse-short-channel effect for circuit simulation

Mitiko Miura-Mattausch; Masami Suetake; Hans Jürgen Mattausch; S. Kumashiro; N. Shigyo; S. Odanaka; Noriaki Nakayama

The proposed threshold-voltage (V/sub th/) model for circuit simulation includes reverse-short-channel effects (RSCE) and short-channel effects (SCE) based on their respective physical origins. A linear vertical-impurity profile approximation for simplified RSCE-modeling already enables 8 mV average V/sub th/-accuracy (max<45 mV) under all bias conditions for source, drain, and bulk for L/sub gate/ down to 0.15 /spl mu/m. The complete V/sub th/-model needs only ten constant L/sub gate/-independent parameters.


international electron devices meeting | 2002

HiSIM: a MOSFET model for circuit simulation connecting circuit performance with technology

Mitiko Miura-Mattausch; Hiroaki Ueno; Masayasu Tanaka; Hans Jürgen Mattausch; S. Kumashiro; Tetsuya Yamaguchi; K. Yamashita; Noriaki Nakayama

Circuit simulation models should be pragmatic, but should be accurate at the same time. HiSIM (Hiroshima-University STARC IGFET Model), aiming to fulfil both requirements, is based on an iterative surface-potential determination in 2D device simulators. However, the essence of each technology is extracted from measurements, thus simplifying modeling procedure and allowing large-scale circuit simulation with 0.1 /spl mu/m-MOSFET technologies.


custom integrated circuits conference | 2001

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability

S. Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Y. Tatsumi; Mitiko Miura-Mattausch; S. Kumashiro; Tetsuya Yamaguchi; K. Yamashita; Noriaki Nakayama

We propose an efficient, test-circuit-based method to determine not only CMOS-device-parameter variations but to simultaneously separate intra-chip from inter-chip variations. The method is demonstrated by using a differential-amplifier stage with feedback coupling as the test-circuit and the drift-diffusion MOSFET model HiSIM for the circuit simulation. The result shows that the proposed test circuit, when constructed only with n-MOSFETs or p-MOSFETs, enables one to separate gate length and channel doping variations as well as their inter- and intra-chip magnitudes in a direct way.


IEEE Transactions on Electron Devices | 2002

Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

Hioraki Ueno; Daisuke Kitamaru; K. Morikawa; Masayasu Tanaka; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; S. Kumashiro; Tetsuya Yamaguchi; K. Yamashita; Noriaki Nakayama

A new threshold voltage (V/sub th/) model has been developed for the pocket-implant technology. The model extracts the threshold condition from the entire mobile charge concentration in the channel with only five additional parameters; the maximum doping concentration (N/sub subp/) of the pocket profile, the penetration length (L/sub p/) into the channel, and three enhanced short-channel parameters. The model reproduces the measured V/sub th/ versus. gate-length (L/sub gate/) characteristics with an average error of a few millivolts under any bias conditions.


international conference on simulation of semiconductor processes and devices | 1999

Precise physical modeling of the reverse-short-channel effect for circuit simulation

Masami Suetake; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; S. Kumashiro; N. Shigyo; S. Odanaka; Noriaki Nakayama

A physical based threshold voltage model for circuit simulation is developed. The conventional short-channel effect as well as the reverse-short-channel effect are included. The reverse-short-channel effect due to impurity pileup at the surface of the substrate is modeled by assuming a linear impurity profile as a function of depth. Measured threshold voltage dependence on the bulk voltage is used to determine the impurity profile. The physically based modeling of the reverse-short-channel effect enabled a short-channel effect description, which simply exploits the channel length dependence of the lateral electric field.


custom integrated circuits conference | 2005

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime

Youichi Takeda; Dondee Navarro; Shingo Chiba; M. Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; S. Kumashiro; S. Miyamoto

MOSFET harmonic distortion characteristics up to the cutoff frequency (fT) are measured and analyzed with the MOSFET model HiSIM. While distortion characteristics at low frequency are determined by carrier mobility, characteristics at high frequency are influenced by the time delay of carriers to form the channel. At low frequency, IP3 values, calculated using a quasi-static model, correspond to values from the conventional method of extraction. For accurate prediction of IP3, non-quasi-static effects become necessary at high-frequency switching above fT/2


international conference on simulation of semiconductor processes and devices | 2006

Analysis and Compact Modeling of MOSFET High-Frequency Noise

T. Warabino; Masataka Miyake; Norio Sadachika; Dondee Navarro; Youichi Takeda; G. Suzuki; Tatsuya Ezaki; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; S. Kumashiro; S. Miyamoto

We have developed a high-frequency noise model for short channel MOSFETs by considering the position dependent surface potential which results in a non-uniform mobility distribution along the channel. The chosen approach successfully reproduces the induced-gate noise and the cross-correlation noise between drain and gate for short channel MOSFETs without additional model parameters. In particular, the gate noise characteristics at GHz frequencies are accurately captured. The newly developed high-frequency noise model is implemented in the complete surface-potential based MOSFET model HiSIM (Hiroshima-university STARC IGFET Model) for circuit simulation


Applied Physics Letters | 2002

Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal–oxide–semiconductor field-effect transistors

Hans Jürgen Mattausch; Masami Suetake; Daisuke Kitamaru; Mitiko Miura-Mattausch; S. Kumashiro; Naoyuki Shigyo; Shinji Odanaka; Noriaki Nakayama

An improved method for extracting the vertical channel-impurity profile [Nsub(x)] of metal–oxide–semiconductor field-effect transistors (MOSFETs) from measured threshold–voltage dependence on bulk–source voltage is proposed. Previous restriction to slowly varying Nsub(x) is overcome by approximating Nsub(x) as a simple analytic function. Application to advanced MOSFETs with steep pileup or retrograded channel profiles and channel length down to 100 nm becomes possible. Extracted analytic profiles are additionally useful for modeling of Nsub(x)-dependent MOSFET phenomena, e.g., the reverse-short-channel effect.


Applied Physics Letters | 2005

Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors

S. Hosokawa; Dondee Navarro; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; S. Kumashiro; S. Miyamoto

The high thermal-drain-noise coefficient γ for short-channel metal-oxide-semiconductor-field-effect transistors (MOSFETs) has little to do with hot electrons or velocity saturation, but is determined by the potential gradient along the channel. Consequently, an analytical model for circuit simulation, derived by integration with the surface-potential distribution along the channel, reproduces measured noise characteristics without additional fitting parameters. Furthermore, experimental and theoretical data suggest a fixed relation between the source-drain voltage (Vds) gradients of γ under the saturation condition and the threshold-voltage shift (ΔVth) relative to a long-channel MOSFET.

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