Witold Machowski

Four-quadrant Analog Multiplier Based On CMOS Inverters

The paper describes a new four-quadrant analog multiplier CMOS implementation based on CMOS inverters and exploiting quadrature technique. An outstanding feature of this circuit solution is suitability for low voltage operation reaching the extreme for the analog part, since there are only two transistors is tacked in between supply rails. The circuit in question is symmetric driven and fully balanced. The operation principle is described as well as simulation results are presented

Mobile user tracking system with ZigBee

In the paper an implementation of mobile nodes tracking system based on ZigBee and Wi-Fi wireless networks is presented. On the base of known algorithmic as well as circuit solutions a simple yet universal system, applied in prototype application dedicated for persons localization in museum premises has been developed. Since system utilizes entirely wireless communication, it can be applied in any closed objects. The system has been preliminarily verified in real in-situ environment.

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.

Hybrid DPWM implementation using coarse and fine programmable ADLL

abstract In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse WidthModulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybridDPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity withpractical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and AnalogDelay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fineprogrammable delay element is used to adjust the delay time of delay line and lock it to required time.The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based onshunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at aswitching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation indexM¼0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) forreal CMOS process are presented.& 2014 Elsevier Ltd. All rights reserved.

Low voltage charge-pump-based VCO circuits using CMOS inverters as building blocks

In the paper a circuit implementation of CMOS voltage controlled oscillator is presented. The most interesting feature of the presented proposal is extreme low voltage suitability, because CMOS inverters are used as main building blocks. The simulation results with real foundry parameters are also included.

Low Voltage Low Frequency Continuous Time CMOS Antialiasing Filters

In the paper design considerations for low frequency antialiasing filters suitable for low voltage modern CMOS technology. Two circuit implementations of Sallen-Key architecture are presented. First uses conventional approach and utilizes long tail pair as amplifying block, while the second exploits CMOS inverters for the same purpose and thus its supply requirements are lower. In both a tricky solution of active resistor formed by transmission gates with long MOSFETs is used. Simulation results are presented and discussed.

CMOS Current Conveyor Design and Macromodel

The paper presents the design of second generation current conveyor (CCII) with low voltage regulated cascade current mirrors in CMOS technology. An accurate nonlinear macromodel of CCII has also been developed and results of simulation at transistor level model and macromodel are presented and compared.

Proposition of the full synchronization method for transmission systems with variable duration of bits

The paper reports the problem of synchronizing clocks in the delta codecs systems with variable length of bits. The original synchronization method, valuable in systems dedicated to transmission the bits with variable time duration was projected and experimentally verified. Performed measures and observations have shown elimination of the synchronization lose phenomenon. Stand on the Spartan 3E evaluation modules, a flexible platform for the implementation the transmission system with non-uniform sampling delta codecs was developed.

Recovery synchronization in ANS-DM demodulator

Adaptive Non-uniform Sampling Delta Modulation (ANS-DM) is one of the waveform coding techniques, where a sampling instant and a quantization step size are adopted. The ANS-DM modulator produces an output binary stream, that caries information about signal and includes necessary information of coder parameters (sampling instant and quantization step). In demodulator this values have to be recovered for proper signal reconstruction. To date, no systematic investigation that considered signal decoding of the delta systems with sampling instant and step size adaptation were extensively analyzed. In the paper the analytical analysis of a parasitic signal oscillations in the reconstructed signal, as a consequence of the recovery synchronization process in ANS-DM demodulator, have been discussed. Drowned conclusions allow improving the quality of received signal transmitted over ANS-DM system in presence of noises in transmission channels.

Class-BD audio amplifiers with common-mode free output

A new topology of the Class-BD amplifier is proposed. It is composed of the typical H-bridge output stage with four MOSFETs controlled by the optimal NBDD PWM signals and two additional switches separating the H-bridge from the power supply during the time intervals in which either high-side or low-side MOSFETs of the H-bridge are closed at the same time. The differential output of the presented amplifier has the same audio performance as that one using the optimal NBDD modulation, moreover, the power MOSFETs creating the new output H bridge are switching at the same frequency as its prototype. The proposed Class-BD amplifier keeps the CM output constant, thereby removing a major contributor to radiated emissions. Basic feasibility study of the proposed configuration has been performed and compared with the configuration of the Class-BD amplifier using CM Free PSCPWM modulation known in literature on the subject. Experimental models of the considered in the paper Class-BD audio amplifiers have been realized using digital audio MOSFETs IRF6775MTRPbF, single-output gate drivers with self-boost charge pump bias supply and with capacitor-based signal isolation for floating single-output gate drivers. Simulation results are presented.