Wojciech Kolodziejski

Current controlled delay line elements' improvement study

The chain of delay elements creating delay lines are the basic building blocks of delay locked loops (DLLs) applied in clock distribution network in many VLSI circuits and systems. In the paper Current Controlled delay line (CCDL) elements with Duty Cycle Correction (DCC) has been described and investigated. The architecture of these elements is based on Switched-Current Mirror Inverter (SCMI) and CMOS standard or Schmitt type inverters. The primary characteristics of the described CCDL element have been compared with characteristics of two most popular ones: current starved, and shunt capacitor delay elements. The simulation results with real foundry parameters models in 180 nm, 1.8 V CMOS technology from UMC are also included. Simulations have been done using BSIM3V3 device models for Spectre from Cadence Design Systems.

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.

Hybrid DPWM implementation using coarse and fine programmable ADLL

abstract In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse WidthModulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybridDPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity withpractical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and AnalogDelay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fineprogrammable delay element is used to adjust the delay time of delay line and lock it to required time.The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based onshunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at aswitching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation indexM¼0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) forreal CMOS process are presented.& 2014 Elsevier Ltd. All rights reserved.

Low voltage charge-pump-based VCO circuits using CMOS inverters as building blocks

In the paper a circuit implementation of CMOS voltage controlled oscillator is presented. The most interesting feature of the presented proposal is extreme low voltage suitability, because CMOS inverters are used as main building blocks. The simulation results with real foundry parameters are also included.

Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD Audio Amplifiers

The paper presents an original architecture and implementation of 9-bit LBDD hybrid DPWM circuit for Class-BD digital audio amplifier. The input PCM signals are directly transformed into 24-bit LBDD DPWM signals and then are requanized to the 9-bit digital outputs using noise-shaping process to support high fidelity with practical values of time resolution, and finally are converted by the DTCs into the two physical trains of 1-bit PWM signals. The architecture of the proposed Class-BD hybrid DPWM circuit is composed of two Class-AD ones. The hybrid quantizer converts 6 MSB bits using counter method, based on the STM32F407xx microcontroller, while the remaining 3 LSB bits – using a method based on the Programmable Tapped Delay Line (PTDL). All necessary time waveforms are generated on the base of the internal microcontroller oscillator 168 MHz. The proposed 9-bit Class-DB DPWM circuit allows to attain SNR of 110 dB and THD about 0,2% within the audio baseband, at switching frequency of 328.1 kHz, clock frequency of 42 MHz and modulation index M = 0.95. Basic verification of algorithm and circuit operation as well as simulation and preliminary experimental results have been performed.

Cancellation of common-mode output signal in Class-BD audio amplifiers

In the paper new topologies of the Class-BD amplifiers with Common-Mode (CM) free outputs have been presented. They are composed of the typical H-bridge output stage with four MOSFETs controlled by the optimal NBDD PWM signals and two additional switches separating the H-bridge from the power supply during the time intervals in which either high-side or low-side MOSFETs of the H-bridge are closed at the same time. The proposed amplifiers have been compared to the Class-BD configuration using the optimal NBDD modulation with respect to audio performance of the differential and CM outputs. Experimental models of the presented in the paper Class-BD audio amplifiers have been realized using digital audio MOSFETs IRF6775MTRPbF, single-output gate drivers with self-boost charge pump bias supply and with capacitor-based signal isolation for floating single-output gate drivers. Intensive SPICE simulations of the real output stage circuits of the proposed Class-BD amplifiers have pointed out that proposed new configurations have similar audio performance as the prototype using optimal NBDD modulation, besides keep the CM outputs constant, thereby removing a major contributor to radiated emissions.

Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL

In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.

Low voltage charge-pump-based Sigma-Delta Modulator using CMOS inverters as building blocks

The paper summarizes a concept of CMOS implementation of a new asynchronous sigma-delta modulator, based exclusively on CMOS inverters (or similar two-transistor blocks) as building blocks. The proposed a SigmaDelta-modulator is extremely suitable for low voltage operation and is fully compatible with digital CMOS, since there are only two transistors stacked in between supply rails. Circuit diagrams of particular functional blocks are presented. Selected simulation results with BSIM3v3 models provided by foundries are reported.