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Dive into the research topics where S.L. Toh is active.

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Featured researches published by S.L. Toh.


IEEE Transactions on Device and Materials Reliability | 2008

In-Depth Electrical Analysis to Reveal the Failure Mechanisms With Nanoprobing

S.L. Toh; P.K. Tan; Y.W. Goh; E. Hendarto; J.L. Cai; H. Tan; Q.F. Wang; Q. Deng; Jeffrey Lam; L.C. Hsia; Z. H. Mai

This paper highlights the use of a localized probing technique, nanoprobing, to reveal some of the subtle defects affecting the yield of integrated circuits in the nanometer generation nodes. The tool is equipped with the capability to isolate and characterize the exact failing transistors of the malfunctioned devices. As a result, the identification process of the failure mechanisms, and hence the root cause, can be accelerated. The electrical characterization at the transistor level also offers an appropriate guide to the required physical analysis that has to be carried out in order to ldquovisualizerdquo the defects. Based on the in-depth diagnosis of the defective site, the three case studies covered in this paper demonstrate the importance of this advanced failure-analysis methodology. For the analysis, static random-access-memory test-chips were used. With that, marginal failures or degradations relating to the ultrathin gate oxides, variations in the resistance of the implanted layers in the substrate, and abnormal passive-voltage-contrast signature were determined.


Journal of Vacuum Science & Technology B | 2005

Strain analysis in silicon substrates under uniaxial and biaxial stress by convergent beam electron diffraction

S.L. Toh; Kian Ping Loh; Chris Boothroyd; Kun Li; C. H. Ang; Lap Chan

A detailed description of the application of the convergent beam electron diffraction (CBED) technique for studying strain propagation in the Si1−xGex∕Si blanket wafers as well as silicon-based metal–oxide–semiconductor field-effect transistors is presented. Specifically, a simple and robust experimental procedure and analysis for silicon lattice strain measurement using the CBED technique is detailed in this article. The use of focused ion beam milling allows for better control of the thickness and site-specific analysis, especially for nanoscaled devices. A pictorial representation of the analytical conditions for the higher order Laue zone lines in CBED patterns is also reported in this work. Based on the Si lattice strain measurement results, we determined that a thin buffer layer of SiOxNy incorporated below the Si3N4 overlay film could render the uniaxial channel strain less compressive. Stress studied on Si1−xGex∕Si blanket wafers reveals that a steeper SiGe compositional gradient would induce larg...


Journal of The Electrochemical Society | 2010

Optimization of AC Electrochemical Etching for Fabricating Tungsten Nanotips with Controlled Tip Profile

S.L. Toh; H. Tan; Jeffrey Lam; Liang-Choo Hsia; Z. H. Mai

AC electrochemical etching in diluted potassium hydroxide (KOH) solution was optimized to fabricate tungsten (W) nanotips with a controllable sharpness and aspect ratio using an additional lift-up step. The final tip profile was dependent on the extent of interaction between the KOH solution and the side of the W surface, and effective bubble shielding effects near the apex region during the lift-up. Lateral etching rate along the W material was affected by parameters such as electrolyte-cathode positioning, etching voltage, and electrode size that influenced the flow or replenishment rate of OH- ions to the W surface submerged in the solution and at the meniscus region. With the lift-up step, the dense layer of bubbles that formed during etching could provide a good shield in minimizing the etch-back effects on the tip apex. Combining the above investigated effects, sharp nanotips with the required aspect ratio could be achieved with the enhanced lateral etching and the protective shield of bubbles.


Electrochemical and Solid State Letters | 2005

Reduction of Local Mechanical Stress in a Transistor Using Si3 N 4 / SiO x N y Contact ESL

S.L. Toh; Kian Ping Loh; C. B. Boothroyd; K. Li; C. H. Ang; E. Er; L. Chan

We have investigated the influence of a contact etch-stop layer (ESL) on the local mechanical stress in a deep sub-micrometer complementary metal oxide semiconductor (CMOS) field-effect transistor using convergent-beam electron diffraction with nanoscale resolution. By introducing a thin buffer layer of SiO x N y underneath the Si 3 N 4 contact ESL, we have shown that the compressive channel strain can be effectively mitigated, resulting in higher electron mobility and drive current in n-channel metal oxide semiconductor field-effect transistors, without undue impact on the electrical performance of p-channel transistors. Hence, the Si 3 N 4 /SiO x N y film stack is a promising alternative for contact ESL to enable high-performance CMOS devices.


international symposium on the physical and failure analysis of integrated circuits | 2008

Application of conductive atomic force microscopy to study the in-line electrical defects

S.L. Toh; Q. Deng; W.T. Tang; V. Lim; F.H. Gn; P.K. Tan; H. Tan; Z. H. Mai; Jeffrey Lam

Selection of optimized electron beam parameters for in-line monitoring is necessary to eliminate false signals. Application of electron beam to detect electrical defects, particularly leakages, for static random access memory (SRAM) cells poses a great challenge as it requires current measurement tool with nanometer resolution to complement it. By correlating the brightness intensity or the gray-level value to the measured current values, we have shown that conductive atomic force microscopy (C-AFM) can overcome this obstacle and can be used to verify the validity of the voltage contrast (VC) captured by HMI eScan3xx Ebeam inspection tool.


international symposium on the physical and failure analysis of integrated circuits | 2007

Use of Nanoprobing as the Diagnostic Tool for Nanoscaled Devices

S.L. Toh; Z. H. Mai; P.K. Tan; E. Hendarto; H. Tan; Q.F. Wang; J.L. Cai; Q. Deng; T.H. Ng; Y.W. Goh; Jeffrey Lam; L.C. Hsia

Nanoprobing plays a crucial role for failure analysis (FA) in the nanometer-region generation nodes by having the capability to detect the failure sites and characterize the electrical behaviour of malfunctional devices for better understanding of the failure mechanisms. It also offers a guide to the necessary physical analysis in identifying the cause of failure. This established electrical failure analysis (EFA) methodology at a localized area helps to accelerate the FA. Its application to few of the front-end issues is highlighted in the paper.


international symposium on the physical and failure analysis of integrated circuits | 2004

High spatial resolution strain measurement of deep sub-micron semiconductor devices using CBED

S.L. Toh; K. Li; C.H. Ang; E. Er; S. Redkar; Kian Ping Loh; Chris Boothroyd; L. Chan

Mechanical stress due to trench isolation and contact etch-stop-layers (ESLs) has been reported to show a marked influence on the electron and hole mobility of nanoscaled MOSFETs. Conventional tools such as micro-Raman spectroscopy and X-ray diffraction for measuring strain are limited in resolution. By using convergent beam electron diffraction (CBED) with nanometer spatial resolution, we have evaluated the mechanical stress induced in deep sub-micron devices by different etch-stop-layers (ESLs) and have demonstrated that the stress along the channel region can be engineered through the implementation of different ESLs.


international symposium on the physical and failure analysis of integrated circuits | 2009

Electrical characteristics of leakage issues caused by defective Ni salicide

S.L. Toh; P.K. Tan; E. Hendarto; Q. Deng; H.B. Lin; Y.W. Goh; L. Zhu; H. Tan; Q.F. Wang; R. He; Jeffrey Lam; L.C. Hsia; Z. H. Mai

Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properties of NiSi. Ni spiking into Si substrate or conductive bridges between silicide on the gate electrodes and that on the source/drain terminals can occur. These effects can be induced or enhanced by stringent layout, stress or process conditions. Its impact can be evident from electrical failure analysis such as nanoprobing and C-AFM, that are useful in identifying the cause of failure.


Electrochemical and Solid State Letters | 2009

Sharpening Conical Tungsten Nanotips in KOH Solution under Laser Irradiation

S.L. Toh; Z. H. Mai; E. Hendarto; H. J. Mak; Jeffrey Lam; Liang-Choo Hsia

Laser-enhanced chemical etching with a 532 nm neodymium-doped yttrium aluminum garnet pulsed laser in KOH solution was used for sharpening conical tungsten nanotips which were prefabricated with a conventional electrochemical etch. The laser irradiation was incident axially on the tip apex. Due to different light absorption mechanisms by objectives in different sizes, the laser irradiation generates a controllable temperature gradient profile from the tip apex to the tip base. In the KOH solution, the etching rate varies with the temperature profile along the tip axis. The tip apex radius was greatly reduced, with the shape and aspect ratio in good control.


international symposium on the physical and failure analysis of integrated circuits | 2008

Investigation of soft fail issue in sub-nanometer devices using nanoprobing technique

E. Hendarto; H.B. Lin; S.L. Toh; P.K. Tan; Y.W. Goh; Z. H. Mai; Jeffrey Lam

With the miniaturization of electronic devices, identifying the root cause of soft failures using physical failure analysis (PFA) techniques has become a more challenging task. By characterizing the electrical behavior of malfunctioned devices, nanoprobing precisely locates defects before any PFA is performed and allows for deeper understanding of the root cause of soft failure issues. Two case studies are presented to demonstrate the effectiveness of nanoprobing in investigating the root causes of soft failures.

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Jeffrey Lam

Chartered Semiconductor Manufacturing

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Z. H. Mai

Chartered Semiconductor Manufacturing

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P.K. Tan

Chartered Semiconductor Manufacturing

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E. Hendarto

Chartered Semiconductor Manufacturing

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H. Tan

Chartered Semiconductor Manufacturing

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Kian Ping Loh

National University of Singapore

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Q. Deng

Chartered Semiconductor Manufacturing

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Chris Boothroyd

Nanyang Technological University

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Q.F. Wang

Chartered Semiconductor Manufacturing

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Y.W. Goh

Chartered Semiconductor Manufacturing

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