S. Mader

Metastable evaporated thin films of CuAg and CoAu alloys—I occurrence and morphology of phases

Abstract Metastable solid solutions of the CuAg and CoAu systems have been prepared by “vapor quenching” i.e. simultaneous vacuum evaporation of the two components onto a substrate held at liquid nitrogen temperature. The films so obtained are studied by resistivity measurements and by transmission electron microscopy and diffraction. The pure metals and dilute alloys are crystalline as deposited, while concentrated alloys (35–65% Ag for CuAg and 25–65% Au for CoAu) are amorphous when deposited on an amorphous substrate but crystalline when deposited onto a pure metal. The resistivity in the asdeposited state is almost independent of composition, but the annealing behavior of the various compositions is quite different. In particular, the high resistivity of the amorphous alloys anneals out in two distinct stages. In the first stage (near 370°K for CuAg and 430°K for CoAu) a transformation from amorphous to a metastable single-phase crystalline solid solution occurs in a narrow temperature range. The second stage, which is broader, involves the transformation to the equilibrium two-phase state. Structures at various stages of anneal are studied in detail by transmission microscopy and diffraction. A qualitative discussion is given of the reasons for the occurrence of the amorphous structure, for its relatively high metastability, and for its transformation first into a single-phase crystalline structure.

Channeling in low energy boron ion implantation

The effects of both planar and axial channeling on the profile of 5‐keV boron ions implanted into (100) oriented silicon wafers are demonstrated. A tilt angle of 12° from the (100) axis in a ‘‘random’’ crystallographic direction is required to minimize the (100) axial channeling tail. It is also shown that the effect of channeling along 100 planar channels produces a negligible addition to the channeling tail, whereas channeling along the (110) planar channels produces a measurable contribution. Implantation through a thin, 8‐nm, thermally grown silicon dioxide layer with the ion beam aligned along the (100) direction produces an ion profile comparable to an offset of 9° in a random direction.

Stress induced dislocations in silicon integrated circuits

Many of the processes used in the fabrication of silicon integrated circuits lead to the development of stress in the silicon substrate. Given enough stress, the substrate will yield by generating dislocations. We examine the formation of stress-induced dislocations in integrated circuit structures. Examples are presented from bipolar and MOS-based integrated circuit structures that were created during developmental studies. The underlying causes of oxidation-induced stress and the effect on such stress of varying oxidation conditions are discussed. The knowledge thus gained is used to explain dislocation generation during the formation of a shallow-trench isolation structure. The importance of ion-implantation processes in nucleating dislocations is illustrated using structures formed by a deep-trench isolation process and a process used to form a trench capacitor in a DRAM cell. The effect of device layout geometry on dislocation generation is also examined. We show how TEM observations can be used to provide more information than solely identifying those process conditions under which dislocations are generated. By combining TEM observations with stress analysis, we show how the sources of stress responsible for dislocation movement can be identified.

Transient enhanced diffusion in arsenic‐implanted short time annealed silicon

An anomalous enhanced diffusion is observed when As‐implanted Si samples are exposed to rapid heating (∼ seconds) from room temperature to temperatures exceeding 1000 °C. This diffusion can be characterized by a low activation energy of ∼1.8 eV and is active during a very short time (≲ 1 s) probably during the rapid heating up of the sample.

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >

The poly‐single crystalline silicon interface

Cross sectional transmission electron microscopy (TEM) reveals an amorphous interfacial region of the order of 2 nm thick between chemical vapor deposition‐(CVD) deposited polycrystalline silicon films and the single‐crystal silicon substrate. The continuity of this region varies from sample to sample and plays an important role in the effects produced by subsequent heat treatment. In cases where this interfacial layer is continuous, the deposited layer remains polycrystalline. When the region is discontinuous, complete epitaxial realignment of the poly is possible. The speed of realignment depends on the implanted arsenic dose and is much greater than reported for undoped films. Various impurities are also observed at the interface and correlate with the character of the interface.

Rapid thermal annealing of boron‐implanted silicon using an ultrahigh power arc lamp

We have used an ultrahigh powered, 100‐kW vortex cooled arc lamp to anneal 75‐mm‐diam 〈100〉 silicon wafers implanted with various doses of 50‐keV B+ and BF+2 ions. Sheet resistivity measurements, secondary ion mass spectrometry, and transmission electron microscopy have been used to characterize the annealed wafers. Standard diffusion coefficients predict little dopant movement in the temperature (∼1200 °C) and time (∼1 s) region we studied. However, boron atoms which have been channeled relatively deep into the silicon and left in interstitial positions move ∼100 nm in ∼1 s at low temperatures, then stop. We presume that they encounter a vacancy and become substitutional. The dopant diffusion rate then is close to equilibrium values, and there is little measurable movement between 900 and 1250 °C. A 3‐s lamp cycle with maximum wafer temperature 1230 °C is sufficient to fully activate a 1014 cm−2 BF+2 implant and leave the material with no extended defects. The dopant half‐width and junction depth are 50 ...

Selective epitaxy base transistor (SEBT)

A bipolar transistor using selective epitaxy for base formation in a double-poly self-aligned structure is presented. The intrinsic base was formed by a selective-epitaxial deposition in place of ion implantation. Such epitaxial base processes are capable of achieving a narrow intrinsic base sheet resistance R/sub bi/ and base-emitter diffusion capacitance c/sub be/ compared to advanced ion-implanted processes. A selective epitaxial base can be simply introduced in advanced double-poly self-aligned processes compared to a nonselective epitaxial layer.<<ETX>>

Self-aligned SiGe-base heterojunction bipolar transistor by selective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I-V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 k Omega / Square Operator and for emitter widths down to 0.4 mu m. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV/sub CBO/ is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV/sub CEO/, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology.<<ETX>>

Self-aligned bipolar epitaxial base n-p-n transistors by selective epitaxy emitter window (SEEW) technology

A bipolar technology which allows for very thin base formation by ultra-high vacuum/chemical vapor deposition (UHV/CVD) epitaxy and very narrow emitter width using selective epitaxial overgrowth is presented. The key step in this selective epitaxy emitter window (SEEW) process is an in situ doped epitaxial lateral overgrowth over a thin and narrow nitride/oxide pad which forms an emitter window in the sublithographic range and provides an extrinsic base contact at the same time. Advantages over conventional double-poly self-aligned technology are the very thin epitaxial base, the formation of the extrinsic base after intrinsic epitaxial base deposition resulting in a guaranteed link-up, and an emitter width in the deep submicrometer range by optical lithography. n-p-n bipolar transistors with 60-nm base width for 75 k Omega / Square Operator intrinsic base resistance and emitter widths down to 0.2 mu m with 0.07- mu m tolerance ( sigma ) have been fabricated using SEEW technology. Nearly ideal I-V characteristics have been achieved for these very narrow emitters. High-yield figures are demonstrated. The SEEW structure can provide very high current density at acceptable power level. >