C.L. Stanis

High-mobility modulation-doped SiGe-channel p-MOSFETs

A novel subsurface SiGe-channel p-MOSFET is demonstrated in which modulation doping is used to control the threshold voltage without degrading the channel mobility. A novel device design consisting of a graded SiGe channel, an n/sup +/ polysilicon gate, and p/sup +/ modulation doping is used. A boron-doped layer is located underneath the graded and undoped SiGe channel to minimize process sensitivity and maximize transconductance. Low-field hole mobilities of 220 cm/sup 2//V-s at 300 K and 980 cm/sup 2//V-s at 82 K were achieved in functional submicrometer p-MOSFETs.<<ETX>>

Identification of perimeter depletion and emitter plug effects in deep-submicrometer, shallow-junction polysilicon emitter bipolar transistors

Two new types of narrow-emitter effects are identified in shallow and narrow-junction polysilicon emitter bipolar transistors. These effects result from a lower doping concentration close to the emitter perimeter of large devices (perimeter depletion effect) or in very-narrow-emitter devices where the polysilicon plugs up the emitter window (emitter plug effect). The consequence is a locally shallower emitter junction which causes a reduced collector current density and a nonideal base current due to a partial overlap of the emitter-base space-charge region with the poly/monosilicon interface. The nonuniform doping in the polysilicon is verified by energy-dispersive X-ray spectroscopy (EDX) measurements. Electrical measurements give a clear indication of the emitter plug effect for two different self-aligned transistor structures, and further evidence is given by a comparison of various poly emitter processes. >

Profile leverage in self-aligned epitaxial Si or SiGe base bipolar technology

The authors have developed a planar, self-aligned, epitaxial Si or SiGe-base bipolar technology and explored intrinsic profile design leverage for high-performance devices in three distinct areas: transit time reduction, collector-base (CB) junction engineering, and emitter-base (EB) junction engineering. High f/sub T/ Si (30-50 GHz) and SiGe (50-70 GHz) epi-base devices were integrated with trench isolation and polysilicon load resistors to evaluate ECL (emitter coupled logic) circuit performance. A 15% enhancement in ECL circuit performance was observed for SiGe relative to Si devices with similar base doping profiles in a given device layout. Minimum SiGe-base ECL gate delays of 24.6 ps (8 mW) were obtained. Lightly doped spacers were positioned in both the EB and CB junctions to tailor junction characteristics (leakage, tunneling, and avalanche breakdown), reduce junction capacitances, and thereby obtain an overall performance improvement.<<ETX>>

Electromigration failure due to interfacial diffusion in fine Al alloy lines

Damage formation at grain boundary junctions has long been recognized as the dominant electromigration failure mechanism in metal lines. We report the results of drift‐velocity experiments on fine lines with no reservoirs and find that the interfacial mass transport, along the edges of the lines, is faster than that along grain boundaries. This causes mass depletion at the cathode end of the line, leading to electromigration failure. The result demonstrates a new failure mechanism due to electromigration in submicron lines with bamboo grain structures.

The thermal stability of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition

The thermal stability of SiGe films deposited by ultrahigh‐vacuum chemical vapor deposition was studied. Various Ge compositional profiles, including boxes, trapezoids, and triangles were examined. Planar‐view transmission electron microscopy was performed following growth and after furnace annealing at 950u2009°C for 30 min to determine the presence and density of misfit dislocations. All profiles showed very similar stability behavior when expressed in terms of the total thickness of the film, heff, and the effective strain present in the layer, eeff. Following the anneal, misfit dislocations were observed when heff exceeded the critical thickness, as defined by Matthews and Blakeslee [J. Cryst. Growth 27, 118 (1974)], by a factor of ∼2.

Self-aligned SiGe-base heterojunction bipolar transistor by selective epitaxy emitter window (SEEW) technology

In the device a SiGe epitaxial base is integrated in a structure which uses in situ doped epitaxial lateral overgrowth for the formation of the emitter window and the extrinsic base contact. Nearly ideal I-V characteristics have been achieved for a base width of 60 nm with an intrinsic base resistance of 4.6 k Omega / Square Operator and for emitter widths down to 0.4 mu m. A DC collector current enhancement factor of 3.1 was obtained relative to a Si homojunction transistor with a 1.25 times higher intrinsic base resistance. The breakdown voltage BV/sub CBO/ is identical for both Si and SiGe devices, even though the collector-base depletion region is partly overlapped with the reduced-bandgap SiGe strained layer. The lower BV/sub CEO/, measured for the SiGe-base transistor, is due to the higher current gain. Based on these results the fabrication of high-speed bipolar circuits that take advantage of SiGe-base bandgap engineering seems possible using selective epitaxy emitter window (SEEW) technology.<<ETX>>

Novel in-situ doped polysilicon emitter process with buried diffusion source (BDS)

An in-situ doped polysilicon emitter process for very shallow and narrow emitter formation and minimum emitter resistance is presented. An in-situ doped film was imbedded between two undoped poly spacer layers as a buried diffusion source (BDS) to reduce the emitter resistance and to form a high-quality poly/monosilicon interface. Transistors with an emitter area of 0.25 mu m*0.25 mu m and with nearly ideal I-V characteristics were fabricated. A cutoff frequency of 53 GHz and a minimum ECL gate delay of 26 ps were achieved using BDS poly emitter transistors with an emitter area of 0.35 mu m*4.0 mu m.<<ETX>>

113-GHz f/sub T/ graded-base SiGe HBT's

Summary form only given. A novel low-thermal cycle process was used to fabricate epitaxial SiGe-base heterojunction bipolar transistors (HBTs) with record unity current gain cutoff frequencies. The process includes an in situ phosphorus-doped polysilicon emitter which requires only a 800 degrees C-10-s anneal. A peak f/sub T/ of 113 GHz at V/sub CB/ of 1 V was obtained for an intrinsic base sheet resistance of 7 k Omega / Square Operator . >

Partial-SOI isolation structure for reduced bipolar transistor parasitics

A bipolar isolation structure with the capability of significantly reducing collector-base capacitance and base resistance is presented. Partial SOI, with SOI surrounding the collector opening, can be used to reduce the collector window width in combination with any emitter-base self-aligned bipolar device structure, and in particular for device structures that feature sublithographic emitter width. Near-ideal transistor Gummel characteristics and a minimum ECL gate delay of 24 ps have been achieved with a nonoptimized lateral device layout, and simulations suggest that sub-20-ps delay at reduced switch current will be possible by using the optimized partial-SOI isolation structure.<<ETX>>

Self-aligned bipolar epitaxial base n-p-n transistors by selective epitaxy emitter window (SEEW) technology

A bipolar technology which allows for very thin base formation by ultra-high vacuum/chemical vapor deposition (UHV/CVD) epitaxy and very narrow emitter width using selective epitaxial overgrowth is presented. The key step in this selective epitaxy emitter window (SEEW) process is an in situ doped epitaxial lateral overgrowth over a thin and narrow nitride/oxide pad which forms an emitter window in the sublithographic range and provides an extrinsic base contact at the same time. Advantages over conventional double-poly self-aligned technology are the very thin epitaxial base, the formation of the extrinsic base after intrinsic epitaxial base deposition resulting in a guaranteed link-up, and an emitter width in the deep submicrometer range by optical lithography. n-p-n bipolar transistors with 60-nm base width for 75 k Omega / Square Operator intrinsic base resistance and emitter widths down to 0.2 mu m with 0.07- mu m tolerance ( sigma ) have been fabricated using SEEW technology. Nearly ideal I-V characteristics have been achieved for these very narrow emitters. High-yield figures are demonstrated. The SEEW structure can provide very high current density at acceptable power level. >