S. Papaioannou

0.48Tb/s (12x40Gb/s) WDM transmission and high-quality thermo-optic switching in dielectric loaded plasmonics

We demonstrate Wavelength Division Multiplexed (WDM)-enabled transmission of 480Gb/s aggregate data traffic (12x40Gb/s) as well as high-quality 1x2 thermo-optic tuning in Dielectric-Loaded Surface Plasmon Polariton Waveguides (DLSPPWs). The WDM transmission characteristics have been verified through BER measurements by exploiting the heterointegration of a 60 μm-long straight DLSPPW on a Silicon-on-Insulator waveguide platform, showing error-free performance for six out of the twelve channels. High-quality thermo-optic tuning has been achieved by utilizing Cycloaliphatic-Acrylate-Polymer as an efficient thermo-optic polymer loading employed in a dual-resonator DLSPPW switching structure, yielding a 9 nm wavelength shift and extinction ratio values higher than 10 dB at both output ports when heated to 90°C.

Optical Cache Memory Peripheral Circuitry: Row and Column Address Selectors for Optical Static RAM Banks

We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10 -9 BER value using two different types of WDM SRAM row Access Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG. A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS block size scaling towards supporting higher-capacity optical SRAM banks.

Tb/s switching fabrics for optical interconnects using heterointegration of plasmonics and silicon photonics: The FP7 PLATON approach

We present recent work that is carried out within the FP7 project PLATON on novel Tb/s switch fabric architectures and technologies for optical interconnect applications, employing heterointegration of plasmonics, silicon photonics and electronics.

On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX s /DEMUX s With 40-GH z Channel Bandwidth

We demonstrate two 8 × 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/ demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being ~12 and ~9 μm, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 μW/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than 18 dB crosstalk and higher than 40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 × 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proofof-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties.

Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

WDM-enabled optical RAM architectures for ultra-fast, low-power optical cache memories

The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.

Eight-channel second-order ring resonator based SOI multiplexers/demultiplexers for optical interconnects

We demonstrate two 8×1 silicon ring-based multiplexers for dual stream multiplexing. All resonances were thermo-optically tuned and spaced by 100GHz having >40GHz bandwidth. Error-free performance without significant signal degradation was obtained for two 4-channel streams at 10Gb/s.