S. R. Whiteley

Data-driven self-timed RSFQ digital integrated circuit and system

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.

Internally shunted sputtered NbN Josephson junctions with a TaNx barrier for nonlatching logic applications

We report on the growth, fabrication, and device characterization of NbN internally shunted Josephson junctions with a TaNx barrier. The resistivity of TaNx films could be varied from a few hundred micro-ohms to a few hundred milliohms by increasing the N2 pressure during reactive sputtering. The temperature dependence of IcRn of the junctions with ∼13 mΩ cm barrier resistivity was measured for various barrier thicknesses. The coherence length of the barrier was determined to be 5 nm. By adjusting the barrier thickness, IcRn values >500 μV were observed up to 8.3 K, with Ic and Rn of magnitudes that are suitable for single-flux-quantum digital circuits.

Monte Carlo and thermal noise analysis of ultra-high-speed high temperature superconductor digital circuits

We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.

Data-driven self-timed RSFQ high-speed test system

Functional testing of rapid single-flux-quantum (RSFQ) logic circuits at high speed is necessary to further optimize circuit design, but it is not easy to do off-chip testing because of the high speed and small amplitude of SFQ pulses. This paper will present the design and test results of an 20 Gb/s bit-by-bit on-chip high-speed digital test system based on data-driven self-timed (DDST) circuits.

Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 /spl mu/m, 0.25 /spl mu/m, and 0.35 /spl mu/m commercial CMOS processes. Their static I-V characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured by using ring oscillators agree well with the simulation results. The experimental results indicate about 40% speedup from 300 K to 4.2 K. A three-transistor DRAM cell for a Josephson-CMOS hybrid memory is also investigated at low temperature. The temperature dependence of the retention time shows an exponential increase at low temperatures. Based on the low-temperature CMOS device model, we have developed short-delay CMOS amplifiers, which would amplify a 40 mV voltage input to CMOS voltage level with the propagation delay of about 100 ps, assuming the use of a 0.18 /spl mu/m CMOS process. We have measured the propagation delay of the CMOS amplifier by using a single-flux-quantum (SFQ) delay measurement system. This is a complete demonstration of the signal exchanges between SFQ and CMOS circuits at 4.2 K.

A 10 GHz digital amplifier in an ultra-small-spread high-J/sub c/ Nb/Al-AlOx/Nb integrated circuit process

We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2 niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

Self-timing and vector processing in RSFQ digital circuit technology

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increases, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists of two self-timed shift registers and an on-chip 8-28-GHz clock generator.

High data rate switch with amplifier chip

A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.

Engineering issues in high-frequency RSFQ circuits

Abstract This paper reports progress on several projects that contribute to advancing the state of the art of rapid single flux quantum (RSFQ) logic. The first project is aimed to demonstrate, with true digital testing, the performance of RSFQ circuits of significant size and importance at a frequency that challenges the best semiconductor circuits, with only a miniscule fraction of their power dissipation. The second is a demonstration of an internally shunted SNS junction that has a high I c R n product and is intended as a drop-in replacement for the now-common resistively shunted tunnel junction; the advantage of this device is reduction of size, minimization of parasitic inductances, as well as high I c R n product for higher frequency operation. In the third project, we are trying to break the memory bottleneck that has long plagued superconductor digital electronics by using a hybrid of Josephson and CMOS technologies.