Xiaofan Meng

Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 /spl mu/m, 0.25 /spl mu/m, and 0.35 /spl mu/m commercial CMOS processes. Their static I-V characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured by using ring oscillators agree well with the simulation results. The experimental results indicate about 40% speedup from 300 K to 4.2 K. A three-transistor DRAM cell for a Josephson-CMOS hybrid memory is also investigated at low temperature. The temperature dependence of the retention time shows an exponential increase at low temperatures. Based on the low-temperature CMOS device model, we have developed short-delay CMOS amplifiers, which would amplify a 40 mV voltage input to CMOS voltage level with the propagation delay of about 100 ps, assuming the use of a 0.18 /spl mu/m CMOS process. We have measured the propagation delay of the CMOS amplifier by using a single-flux-quantum (SFQ) delay measurement system. This is a complete demonstration of the signal exchanges between SFQ and CMOS circuits at 4.2 K.

A 10 GHz digital amplifier in an ultra-small-spread high-J/sub c/ Nb/Al-AlOx/Nb integrated circuit process

We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2 niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

Light-anodization process for high-J/sub c/ micron and submicron superconducting junction and integrated circuit fabrication

We have developed a new approach for high critical current density (J/sub c/) small junction fabrication. The key step is light anodization that forms a thin double-layer of Al/sub 2/O/sub 3//Nb/sub 2/O/sub 5/ oxides around the junction area and on the sidewalls of the junction. This anodization ring is a good dry-etch stop, so the via for the junction contact can be larger than the junction area. The anodization ring can also protect the junction from plasma damage during dry etching and sputtering steps; therefore, it can reduce the junction leakage current and critical-current spread. The new technique is very simple and cost effective compared with the CMP approach. It needs only one additional mask and process step. We have used the technique to fabricate high-J/sub c/ submicron Nb/Al-AlO/sub x//Nb tunnel junctions with very low critical-current spreads. Using this technique, we have also fabricated Nb SQUIDs and various Nb digital ICs.

Very small critical current spreads in Nb/Al-AlOx/Nb integrated circuits using low-temperature and low-stress ECR PECVD silicon oxide films

We have developed a new Nb/Al-AlOx/Nb IC process with very small critical current spread. Low-temperature and low-stress ECR (Electron Cyclotron Resonance) PECVD (Plasma Enhanced Chemical Vapor Deposition) silicon oxide films have been used in the Nb IC process for all dielectric insulating layers to replace e-beam evaporated silicon monooxide films and RF reactive sputtered silicon oxide. Since ECR PECVD silicon oxide films have superiority in quality over e-beam evaporated silicon monooxide films and extremely low damage to underlayers compared to sputtered films, our Nb/Al-AlOx/Nb IC quality and yield have been improved greatly. The critical current spreads (maximum to minimum) are less than 1%(/spl sigma/<0.2%) on chip and less than 4%(/spl sigma/<0.7%) cross a four-inch wafer for 5 /spl mu/m/spl times/5 /spl mu/m junctions. Even for high critical current density (/spl sim/10 kA/cm/sup 2/) small junctions (1.5 /spl mu/m x 1.5 /spl mu/m) the on-chip spread is only about 4%(/spl sigma/<0.7%). High quality Nb/Al-AlOx/Nb ICs have been fabricated and demonstrated.

Internally shunted Josephson junctions with barriers tuned near the metal–insulator transition for RSFQ logic applications

The fabrication of self-shunted SNS (superconductor/normal conductor/superconductor) Josephson junctions for rapid single flux quantum (RSFQ) logic could potentially facilitate increased circuit density, as well as reduced parasitic capacitance and inductance over the currently used externally shunted SIS (superconductor/insulator/superconductor) trilayer junction process. We report the deposition, fabrication, and device characterization of Josephson junctions prepared with Nb1?yTiyN electrodes and TaxN barriers tuned near the metal?insulator transition, deposited on practical large-area oxide-buffered silicon wafers. When scaled to practical device dimensions, this type of junction is found to have an IcRn product of over 0.5?mV and a critical current (Ic) and normal resistance (Rn) of magnitudes suitable for single flux quantum digital circuits. A longer than expected normal-metal coherence length (?n) of 5.8?nm is inferred from the thickness dependence of Jc at 4.2?K for junctions fabricated using a barrier resistivity of 13?m??cm. Although not well understood and not quantitatively predicted by conventional theories, this results in a sufficiently high Ic and IcRn to make the junctions suitable for practical applications. Similar observations of unexpectedly large Josephson coupling currents in SNS junctions have been documented in other systems, particularly in cases when the barrier is near the M?I transition, and have become known as the giant proximity effect. The temperature dependence of ?n, IcRn, and Jc are also reported. For this technology to be used in practical applications, significant improvements in our fabrication process are needed as we observe large variations in Ic and Rn values across a 100?mm wafer, presumably as a result of variations in the Ta:N stoichiometry and the resulting changes in the TaxN barrier resistivity.

Engineering issues in high-frequency RSFQ circuits

Abstract This paper reports progress on several projects that contribute to advancing the state of the art of rapid single flux quantum (RSFQ) logic. The first project is aimed to demonstrate, with true digital testing, the performance of RSFQ circuits of significant size and importance at a frequency that challenges the best semiconductor circuits, with only a miniscule fraction of their power dissipation. The second is a demonstration of an internally shunted SNS junction that has a high I c R n product and is intended as a drop-in replacement for the now-common resistively shunted tunnel junction; the advantage of this device is reduction of size, minimization of parasitic inductances, as well as high I c R n product for higher frequency operation. In the third project, we are trying to break the memory bottleneck that has long plagued superconductor digital electronics by using a hybrid of Josephson and CMOS technologies.

Micron and submicron Nb/Al-AlO/sub x//Nb tunnel junctions with high critical current densities

To increase superconducting IC speed and density, it is necessary to reduce junction size and increase critical current density. We describe the fabrication and properties of high critical current density micron and submicron Nb/Al-AlO/sub x//Nb tunnel junctions. Using a 10:1 reduction wafer stepper with I-line photoresist, we obtained a minimum linewidth of 0.6 /spl mu/m and junctions as small as 0.3 /spl mu/m/sup 2/. The critical current densities can be as high as 20 kA/cm/sup 2/ still with low subgap currents. The measured critical current spreads are small. This is due to the use of low-temperature, low-stress ECR (Electron Cyclotron Resonance)-based PECVD (Plasma Enhanced Chemical Vapor Deposition) SiO/sub 2/ insulation layers and light anodization around junction areas. The junctions have potential applications in very high-speed superconducting digital circuits and submillimeter microwave devices.

RSFQ multiplexer and demultiplexer

An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and outputs of the DEMUX are complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single output. The complementary output is recovered from the output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.

Josephson-CMOS hybrid memory with ultra-high-speed interface circuit

In this paper we report our recent progress in realizing a Josephson-CMOS hybrid random-access memory. We have established a 4 K CMOS device model based on low-temperature experimental data on discrete MOS devices. We implemented an ultra-high-speed interface circuit to amplify millivolt-level Josephson input signals to volt-level signals for CMOS circuits. The interface circuit includes a Josephson series-array preamplifier and an ultra-fast hybrid Josephson-CMOS amplifier. Simulation and optimization of the interface circuit have predicted a delay of less than 60 ps. We have designed and fabricated the interface circuit using the 0.25 /spl mu/m National Semiconductor Corporation (NSC) process for the CMOS chip, and the UC Berkeley 6.5 kA/cm/sup 2/ Nb process for the Josephson junction (JJ) chip. The functionality of the interface circuit has been tested and proved by wire-bonding the CMOS chip to the JJ chip. We also demonstrate the design and fabrication of a model 64-kbit Josephson-CMOS hybrid memory; this circuit includes the ultra-high-speed interface, address buffers, word line decoders, 3 T DRAM-type cells, and Josephson sensing circuits; these are fabricated using the 0.25 /spl mu/m NSC CMOS process and the UC Berkeley Nb process. Subnanosecond access time is predicted by a conservative simulation that used a room-temperature model for the CMOS. We plan a stacked-chip structure using very short wire bonding with which we will be able to measure subnanosecond access times.