S. Ravi

Design of Low-Power Multiplier Using UCSLA Technique

Multiplication is one of the major fundamental operations and key hardware blocks in any digital system. This paper presents the comparison of the VLSI design of uniform carry select adder (UCSLA)-based multiplier technique with the variable carry select adder (VCSLA)-based multiplier technique. The analysis is carried out on the different bit sized values of unsigned inputs, and output results show that the area, power, and delay are reduced in the UCSLA-based multiplier technique compared to VCSLA-based technique. The timing delay in 64-bit VCSLA-based multiplier technique is 95.25 ns for performing the multiplication, which is reduced by 11.11 % in the UCSLA-based multiplier technique. In the same manner, area is reduced by 39.42 % and power also reduced by 19.28 % in UCSLA-based multiplier technique. The simulation works of multipliers are carried out in Verilog-HDL (Modelsim). After the simulation, the results are obtained using cadence tool.

Design of optimal final adder for parallel multiplier

The partial products in the normal multiplier is produced from the product of multiplier and the multiplicand, when considering the partial products the middle order take more time for final addition than considering the left and right side of the partial products, So to reduce the middle order partial product delay taking the optimal adder which is having high speed, on considering the BEC-1 adders Which has 3 types of architecture namely EBS, SBS and VBS. Analysis has been made on these adders both manually and experimentally to find out the optimal one in area, delay and power wise and to implement that as the final adder in the high delay path region. The experimental work has been done in typical case 180 nm technology for analyzing area, delay, power for BEC-1 adders. On analysis EBS shows better result manually and experimentally, So putting EBS adder in a unsigned multiplier using DADDA algorithm shows better result.

Design and implementation of SoC Wire Codec for space applications

Dynamic Partial Reconfiguration (DPR) permits a particular portion of an FPGA to be reconfigured while the remaining part continues to operate. In order to communicate between static (which is running during the whole application runtime and stores all critical interfaces ) and dynamic regions we propose dedicated Network-on-Chip (NoC) approach called System-on Chip (SoC) Wire. This SoC Wire provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros which suffers from more area and power consumptions. In this paper we designed the SoC Wire Codec by using Verilog HDL code. The implementations have been done using XILINX FPGA platform and the functionality of the system is verified using Modelsim simulation and board level ChipScope PRO. The presented SoC Wire Codec design utilizes 13% reduced area and ultimately reducing cost of the design.