S.S. Tsao

High-temperature silicon-on-insulator electronics for space nuclear power systems: requirements and feasibility

The authors performed a study to determine whether silicon very large-scale integrated circuits (VLSICs) can survive the high temperature (up to 300 degrees C) and total-dose radiation environments (up to 10 Mrad over a 7-10-y system life) projected for a very-high power space nuclear reactor platform. It is shown that circuits built on bulk epitaxial silicon cannot meet the temperature requirement because of excessive junction leakage currents. However, circuits built on silicon-on-insulator (SOI) material can meet both the radiation and temperature requirements. It is also found that the temperature dependence of the threshold voltage of the SOI transistors is less than that of bulk transistors. Survivability of high-temperature SOI VLSICs in space, including immunity to transient and single-event upset, is also addressed. >

Porous silicon techniques for SOI structures

The two principal silicon-on-insulator fabrication techniques are examined. The first is by buried porous Si formation; areas surrounding device islands are converted into porous Si by proper tailoring of the wafer dopant profile. It is known as FIPOS (full insulation by porous oxidized silicon). The second is by epitaxy on porous Si; a uniform surface porous Si layer is used as a seeding layer for low-temperature epitaxy of the device Si. Oxidation of the underlying porous Si layer, via trenches in the device Si, has been improved to the point that defect generation and wafer warpage are avoided. Fabrication of advanced devices on the FIPOS material has shown that the porous silicon technology is among the front-runners for high-performance CMOS LSIs.

Total-dose hardness assurance issues for SOI MOSFETs

The top-gate, back-gate, and sidewall responses of SIMOX and ZMR SOI/MOS transistors to 10-keV X-ray and Co-60 irradiation are compared. For top-gate and sidewall insulators, Co-60 and 10-keV X-ray irradiations at matched dose rates lead to nearly identical responses. Back-gate response, on the other hand, depends strongly on radiation energy and buried insulator thickness. Different X-ray to Co-60 correlation factors can be observed for other technologies with different sidewall and buried insulator materials and thicknesses. It is demonstrated that it is not possible to define a generic set of worst-case radiation bias conditions for all SOI technologies, as back-gate radiation response can be a strong function of transistor drain bias during exposure. However, the magnitude of this effect can vary with material and device processing, and the detailed changes in Si island potential and insulator electric fields that cause this behavior are not yet understood. Postirradiation effects are also addressed briefly. >

Ion-irradiation control of photoluminescence from porous silicon

Ion irradiation was used to pattern a region of red‐light emitting porous silicon by eliminating visible‐light photoluminescence (PL). The PL peak wavelength is approximately 735 nm and shows little dependence on the excitation‐light wavelength. The ratio of PL intensities for different excitation wavelengths was shown to be proportional to the ratio of the absorption coefficients. Below saturation, the integrated PL intensity increased linearly with excitation‐light power density.

Selective porous silicon formation in buried p+ layers

We report a systematic microstructural study of enhanced lateral porous silicon formation in the buried p+ layers of n/p+/p− and p−/p+/p− structures. We find, surprisingly, extremely selective porous silicon formation due to the thin p+ layer in both structures, despite the absence of a p‐n junction in the p−/p+/p− structure. The interface between the isolated island and the buried porous silicon layer was always located at the depth where the net p‐type dopant concentration was 1–8×1015/cm3. The observed microstructure can largely be understood in terms of a recent model for porous Si formation in uniformly doped Si, proposed by Beale et al. [J. Cryst. Growth 73, 622 (1985)]. However, we also observe, for the first time, important effects unique to a nonuniform dopant concentration.

Porous Silicon Formation in N−/N+/N− Doped Structures

This paper examines how dopant profile and anodization conditions affect the formation of buried porous silicon layers in n{sup {minus}}/n{sup +}/n{sup {minus}} doped wafers. Wafers with peak n{sup +} donor concentration {le}10{sup 18}/cm{sup 3} exhibit stray dendritic pores propagating from the n{sup +} layer into the n{sup {minus}} layers. depending on the anodization conditions these larger diameter dendritic pores can even penetrate the entire upper n{sup {minus}} layer, making it unusable for silicon-on-insulator device applications. Lower anodization voltages produce shorter dendrite lengths. Wafers with peak n{sup +} donor concentration {ge}3 {times} 10{sup 18}/cm{sup 3} exhibit negligible stray dendritic pores. In these wafers the buried porous silicon layer is confined only to areas with doping level {ge}1-2 {times} 10{sup 17}/cm{sup 3}. These results should help in optimizing n{sup {minus}}/n{sup +}/n{sup {minus}} doping profiles and anodization conditions for silicon-on-insulator device applications.

Radiation-Tolerant, Sidewall-Hardened SOI/MOS Transistors

Total dose radiation effects were measured for sidewall-hardened n-channel SOI/MOS transistors, fabricated in zone-melt-recrystallized (ZMR) and oxygen-implanted (SIMOX) SOI materials. We compare the radiation responses of transistors with three types of sidewall or edge configurations: island transistors with passivated edges, island transistors without passivated edges, and edgeless (enclosed-gate) transistors. Data from these three test devices allow clear separation of front-, back-, and edge-channel conduction. Passivated edge channels were hard to Co-60 doses in excess of 24 Mrad(Si). The overall hardness of the passivated-edge transistors is limited only by the radiation-induced threshold voltage shifts (about -1 V at 1.0 Mrad) of the top channel. No significant differences in total-dose response of ZMR and SIMOX devices were observed under the radiation conditions employed.

Porous silicon oxynitrides formed by ammonia heat treatment

Porous silicon and its oxide can be converted into porous silicon oxynitrides by ammonia heat treatment. For example, ammonia treatment at 1000 °C for 1 h following 850 °C, 30‐min steam oxidation of porous silicon can result in up to 40 at. % nitrogen in the porous oxynitrides. These porous silicon oxynitrides are compositionally more uniform than ammonia‐nitrided thermal oxides which exhibit nitrogen buildup at the oxide layer interfaces. However, the order of the oxidation and nitridation treatment matters: nitrided oxidized porous silicon exhibits higher electrical breakdown strength than nitrided porous silicon or oxidized nitrided porous silicon.

Multilevel Porous Silicon Formation

Oxidized porous silicon is the basis for one of the frontrunning silicon-on-insulator (SOI) fabrication techniques. Recently, it has also been demonstrated that porous silicon can be metallized to form silicon-on-conductor (SOC) structures. If a method for forming multilevel stacks of porous silicon layers (PSLs) can be developed, it should also be possible to combine the SOI and SOC techniques to form a buried, insulated conductor under single crystal silicon. In this communication, the authors report such a method for multilevel PSL formation.

Microstructure of pores in n+ silicon

Abstract The structure of pores in n−1/n+/n− silicon structures has been studied by cross-section transmission electron microscopy. Under the experimental conditions examined, the pore directions in the n+ layer follow the current path and do not show crystallographic preference. Stray pores were observed in the n− layer and they appear to grow along 〈100〉 directions. By using cross sections transverse to the pore length, we have obtained end-on views that show that the pore walls tend to facet along {111} planes. We have also observed wafer surface faceting on {113} planes as a result of the anodization process.