S. Zoll

Effective work function engineering by sacrificial lanthanum diffusion on HfON-based 14 nm NFET devices

In this paper, the impact of metallic lanthanum (La) deposited by Radio-Frequency PVD on effective work function (WFeff) of HfON-based NFET devices in a sacrificial metal gate-first approach is evaluated for the first time. Engineering of WFeff towards N+ without leakage degradation is demonstrated by tuning both the pedestal TiN thickness and the as-deposited metallic La dose. WFeff shift is related to a La-induced interfacial dipole (5), whose value has been correlated to the effective La dose into HfON/SiON stack after diffusion annealing, which has been accurately measured through a spectroscopic method based on La X-Ray Fluorescence (XRF).

Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2 plasma is not efficient enough to suppress the residue completely [6], and the CH4 treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

Oxygen Control for Wet Clean Process on Single Wafer Platform

Wet processing with low oxygen content may provides some advantages, however, full control to avoid oxygen uptake during wafer processing remains a challenge for short process industrialization on single wafer tool. Inline oxygen concentration monitoring was used for process optimization. Then, cobalt etch in diluted HF solutions was evaluated depending on the recorded oxygen concentration and hardware available options for atmosphere control in the process chamber.

TiN Hard Mask Cleans with SC1 Solutions, for 64nm Pitch BEOL Patterning

Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO2 & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

Cobalt compatible cleaning solutions for 14nm and beyond

In this paper, wet cleaning solution compatible with cobalt are investigated to achieve low Co etching rate on blankets film and no film attack on patterned 14nm wafer after line and via etching. Proposed solutions are compared to conventional wet cleaning solutions.