Sachin Rao

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer

Voltage-controlled oscillator (VCO) based analog-to-digital conversion presents an attractive means of implementing high-bandwidth oversampling ADCs [1,2]. They exhibit inherent noise-shaping properties and can operate at low supply voltages and high sampling rates [1-3]. However, usage of VCO-based ADCs has been limited due to their nonlinear voltage-to-frequency (V-to-F) transfer characteristic, which severely degrades their distortion performance. Digital calibration is used to combat nonlinearity in an open-loop VCO-based ADC, but 1st-order noise-shaping mandates high OSRs, thus increasing power dissipation in digital circuits, even in a nanometer-scale CMOS process [1]. In [2], nonlinearity is suppressed by embedding the VCO in a ΔΣ loop. While this technique works in principle, the need for large loop gain at high frequencies makes it very difficult to achieve high SNDR. For instance, the suppression level near the band edge is approximately 20dB for a VCO-based 2nd-order modulator operating with an over-sampling ratio (OSR) of 30. Our ADC overcomes the impact of VCO non-linearity by minimizing the input signal processed by the VCO. The prototype achieves 78.3dB SNDR in a 10MHz signal bandwidth at 600MHz sampling rate, while consuming 16mW power.

A 16-mW 78-dB SNDR 10-MHz BW CT

This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCOs V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time ΔΣ loop. Using only a first order loop filter, the proposed ΔΣ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

\Delta \Sigma

This paper presents a digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCOs nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. Like many other VCO-based ADCs, the proposed technique does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties. Implemented in a 90 nm CMOS process, the on-chip calibration improves SNDR of an open-loop VCO-based ADC from 46 dB to more than 73 dB in 5 MHz signal bandwidth while consuming 4.1 mW power. The ADC achieves a figure-of-merit of 91-112 fJ/conv-step for different input frequencies.

ADC Using Residue-Cancelling VCO-Based Quantizer

This paper presents circuit techniques to improve the efficiency of high-current LED drivers. An error-averaged, senseFET-based current sensing technique is used to regulate the LED current accurately. Because the proposed scheme eliminates the series current-regulation element present in all conventional LED drivers, it greatly improves efficiency and reduces cost. The converter operates in three different operating modes, namely buck, buck-boost, and boost modes, and achieves high efficiency over the entire Li-Ion battery range (3-5.5 V). Fabricated in 0.5-μm CMOS process, the prototype occupies an active area of 5 mm2. At 1.2-A LED current, the driver achieves an efficiency improvement of over 13% compared to current-regulation-element-based LED drivers. Measured LED current accuracy is better than 2.8% over the entire range of the battery and its standard deviation measured across seven devices is less than 1.6%. The peak efficiencies are 90.7% and 86% at 600-and 1200-mA currents, respectively.

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

A high-resolution time-to-digital converter (TDC) using switched-ring oscillators (SROs) is presented. Leveraging oversampling and noise shaping, the proposed SRO-TDC achieves high resolution without the need for calibration. Ring oscillators are switched between two frequencies to achieve noise shaping of the quantization error in an open-loop manner. By decoupling the sampling clock and input carrier frequencies, SRO-TDC is capable of operating at high oversampling ratios (OSRs). This paper also discusses different noise sources and quantization/device noise tradeoffs in noise-shaping TDCs and presents techniques to characterize TDC linearity, range, and noise performance. Fabricated in 90 nm CMOS technology, the proposed TDC operates over a wide range of input carrier frequencies (0.6-750 MHz) and sampling rates (50-750 MS/s). At 500 MS/s and 80 MHz carrier frequency, it achieves an integrated noise of 315 fs in a 1 MHz bandwidth while consuming 1.5 mW from a 1 V supply. The SRO-TDC occupies an active die area of only 0.02 mm2.

A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique

A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18µm CMOS, at 10mA load current, the prototype achieves a PSR of −50dB and −25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators—Analysis, Design, and Measurement Techniques

High-current LED drivers suffer from a significant efficiency loss due to the presence of a current regulation element (CRE) in series with the LED. In a conventional driver, either a series current source [1] or a sense resistor [2, 3] acts as a CRE to regulate the LED current (ILED). In this paper, we seek to improve the efficiency by eliminating the series CRE. To this end, we employ a highly accurate current sensing scheme to directly regulate ILED and achieve more than 13% efficiency improvement.

A high-PSR LDO using a feedforward supply-noise cancellation technique

This paper presents a voltage-controlled oscillator (VCO) based current to digital converter for sensor readout applications. Second order noise shaping of the quantization error is achieved by using implicit capacitance of the sensor to realize a passive integrator and a VCO-based quantizer. The non-linearity in voltage to frequency conversion of the VCO is tackled by placing the VCO in a loop consisting of a simple digital IIR filter and a passive integrator. The IIR filter provides large gain within the signal bandwidth and suppresses VCO input swing. As a result, non-linearity of the VCO is not exercised, thus greatly improving the proposed architectures immunity to VCO nonlinearity. The use of a digital filter instead of an analog loop filter eases the design and makes it scaling friendly. Designed for an ambient light sensor application, the proposed circuit achieves 900 pA accuracy over an input current range of 4 μA. Fabricated in a 0.18 μm CMOS process, the readout circuit consumes a total of 77.8 μA current, and occupies an active area of 0.36 mm2.

A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing

A hysteretic buck converter employs a hybrid voltage/current mode control to regulate output voltage and switching frequency independently. Fabricated in a 130nm CMOS process, the prototype consumes only 50μA quiescent current and operates at a constant switching frequency of 1MHz over a wide range of output voltages (0.7-to-1.8V) and inductor values (1-to-5μH) with a peak efficiency of 93%. The output ripple and the settling time of the converter are less than ±2.5mV and 10μs, respectively.

A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications

Time-to-digital converters (TDCs) were historically used in laser range-finding, automatic test equipment, and timing jitter measurements, but recent developments in the design of high-resolution TDCs have paved the way for mostly digital implementation of PLLs and ADCs. We present a highly digital switched ring oscillator based TDC (SRO-TDC) that achieves noise shaping and is capable of operating at high OSRs. The prototype SRO-TDC achieves an integrated noise of 315fsrms in a 1 MHz signal band-width at an input carrier and sampling frequencies of 80MHz and 500MHz, respectively while consuming less than 2mW from a 1V supply. It is also capable of operating over a wide range of input carrier frequencies (0.6 to 750MHz) and sampling rates (50 to 750MS/S).