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Dive into the research topics where Qadeer A. Khan is active.

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Featured researches published by Qadeer A. Khan.


international conference on vlsi design | 2006

A single supply level shifter for multi-voltage systems

Qadeer A. Khan; Sanjay K. Wadhwa; Kulbhushan Misri

This paper presents design and application of a level shifter circuit which works with a single power supply. Unlike the conventional level shifter circuits, the proposed level shifter can shift any voltage level signal to a desired higher level without any leakage current. Use of single supply level shifter greatly reduces the supply routing and layout congestion within the chip when level shifting is required between different voltage domains. It also reduces pin count if level shifting is required between two or more chips operating at different supply voltages in a multi-voltage system. The proposed circuit is generic in nature and the voltage range at which level shifting can be done is limited by the technology only. The circuits was designed in 90nm CMOS technology and simulated in SPICE. The simulation results show that the proposed level shifter circuit is able to shift the input signal from 1.2V to 2.5V at maximum frequency of 500MHz.


international symposium on low power electronics and design | 2003

Low power startup circuits for voltage and current reference with zero steady state current

Qadeer A. Khan; Sanjay K. Wadhwa; Kulbhushan Misri

A class of new startup circuits for Voltage and Current Reference circuits are proposed. Unlike conventional startup circuits, the proposed circuits completely turn off once the reference circuit is started and consume no current during normal operation of the reference circuits. The circuits employ feedback from the reference circuit to ensure that the reference circuit has reached its desired operating state prior to shutting themselves off. The proposed circuits are quite useful in low power integrated circuit design. Very low startup time can be achieved. The circuits are generic in nature and can be used with any reference circuit such as bandgap voltage reference, ΔVgs/R circuit, etc.


IEEE Journal of Solid-state Circuits | 2011

A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique

Sachin Rao; Qadeer A. Khan; Sarvesh Bang; Damian Swank; Arun Rao; William J. McIntyre; Pavan Kumar Hanumolu

This paper presents circuit techniques to improve the efficiency of high-current LED drivers. An error-averaged, senseFET-based current sensing technique is used to regulate the LED current accurately. Because the proposed scheme eliminates the series current-regulation element present in all conventional LED drivers, it greatly improves efficiency and reduces cost. The converter operates in three different operating modes, namely buck, buck-boost, and boost modes, and achieves high efficiency over the entire Li-Ion battery range (3-5.5 V). Fabricated in 0.5-μm CMOS process, the prototype occupies an active area of 5 mm2. At 1.2-A LED current, the driver achieves an efficiency improvement of over 13% compared to current-regulation-element-based LED drivers. Measured LED current accuracy is better than 2.8% over the entire range of the battery and its standard deviation measured across seven devices is less than 1.6%. The peak efficiencies are 90.7% and 86% at 600-and 1200-mA currents, respectively.


international solid-state circuits conference | 2011

A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing

Sachin Rao; Qadeer A. Khan; Sarvesh Bang; Damian Swank; Arun Rao; William J. McIntyre; Pavan Kumar Hanumolu

High-current LED drivers suffer from a significant efficiency loss due to the presence of a current regulation element (CRE) in series with the LED. In a conventional driver, either a series current source [1] or a sense resistor [2, 3] acts as a CRE to regulate the LED current (ILED). In this paper, we seek to improve the efficiency by eliminating the series CRE. To this end, we employ a highly accurate current sensing scheme to directly regulate ILED and achieve more than 13% efficiency improvement.


international conference on vlsi design | 2006

Techniques for on-chip process voltage and temperature detection and compensation

Qadeer A. Khan; Siddhartha Gk; Divya Tripathi; S. Kumar Wadhwa; Kulbhushan Misri

This paper presents techniques to detect process, voltage and temperature (PVT) variations in an integrated circuit chip and wafer. Conventional techniques are limited to detection of process variations in which the MOS devices (NMOS and PMOS) move in similar direction i.e. fast n-fast p or slow n-slow p. The presented techniques can be used to compensate skewed variations on the chip i.e. fast n-slow p or slow n-fast p thus increasing the utilization (yield) of the wafer. The proposed techniques can be implemented in any standard CMOS process and can easily be integrated with any circuit requiring PVT compensation. Major applications of these circuits are in I/O drivers and PVT sensitive analog circuits. For I/O drivers, simulation results show that the rise/fall time variation with PVT has been reduced to more than half using the proposed circuits.


radio frequency integrated circuits symposium | 2010

A self-healing 2.4GHz LNA with on-chip S 11 /S 21 measurement/calibration for in-situ PVT compensation

Karthik Jayaraman; Qadeer A. Khan; Baoyong Chi; William Beattie; Zhihua Wang; Patrick Chiang

This paper presents a 2.4GHz, reconfigurable RF LNA using on-chip peak detection and calibration to measure and optimize its input impedance (S11) and gain (S21) in-situ, compensating for the unpredictable effects of process, voltage and temperature (PVT) variations. Measurement results show that the calibration of the LNA across PVT corners improves the S11 by 5.1dB, S21 by 3dB, while not significantly degrading the Noise Figure (0.22dB degradation) and linearity (1.7dBm degradation).


symposium on vlsi circuits | 2012

A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control

Qadeer A. Khan; Amr Elshazly; Sachin Rao; Rajesh Inti; Pavan Kumar Hanumolu

A hysteretic buck converter employs a hybrid voltage/current mode control to regulate output voltage and switching frequency independently. Fabricated in a 130nm CMOS process, the prototype consumes only 50μA quiescent current and operates at a constant switching frequency of 1MHz over a wide range of output voltages (0.7-to-1.8V) and inductor values (1-to-5μH) with a peak efficiency of 93%. The output ripple and the settling time of the converter are less than ±2.5mV and 10μs, respectively.


international symposium on circuits and systems | 2006

A sequence independent power-on-reset circuit for multi-voltage systems

Qadeer A. Khan; G. K. Siddhartha

With the advent of multiple supply domains on a single chip, issues related to power sequencing are becoming a major hurdle for system designers. Existing POR strategies fail to cope up with these issues. We propose a scheme in which the power on reset generation is independent of the sequence of supply ramp-up. The circuit implementation of the proposed methodology has been realized for a dual supply system. The basic circuit is modified so as to consume zero static current. An attempt to reduce any leakage current during supply ramp-up has also been made successfully. Simulation results verify the sequence independence concept and low power consumption. Further the proposed realization is modular enough to be extended for more number of supplies


international conference on vlsi design | 2003

A low voltage switched-capacitor current reference circuit with low dependence on process, voltage and temperature

Qadeer A. Khan; Sanjay K. Wadhwa; Kulbhushan Misri

A low voltage switched-capacitor circuit that generates an almost constant reference current across process, voltage and temperature (PVT) is proposed. The reference voltage is generated by a low voltage band-gap circuit. The output reference current is obtained by applying the generated reference voltage to a low voltage V-I converter. The resistor in the proposed V-I converter is further replaced by a switched capacitor resistor. Due to less variation in the capacitor value across PVTs and high accuracy in integrated voltage reference, the output reference current remains fairly constant. The circuit has been designed in 0.13 /spl mu/m CMOS process at 1.5 V supply voltage. The simulation results show that the output reference current is quite insensitive to PVT and varies linearly with clock frequency and capacitor value of the switched capacitor resistor.


IEEE Journal of Solid-state Circuits | 2015

High Frequency Buck Converter Design Using Time-Based Control Techniques

Seong Joong Kim; Qadeer A. Khan; Mrunmay Talegaonkar; Amr Elshazly; Arun Rao; Nathanael Griesert; Greg Winter; William J. McIntyre; Pavan Kumar Hanumolu

Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or G m-C integrators while a delay line is used to perform voltage to time conversion and to sum time signals. A simple flip-flop generates pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for wide bandwidth error amplifier, pulse-width modulator (PWM) in analog controllers or high resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in small area and with minimal power. Fabricated in a 180 nm CMOS process, the prototype buck converter occupies an active area of 0.24 mm2, of which the controller occupies only 0.0375 mm2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6 V to 1.5 V with 1.8 V input voltage. With a 500 mA step in the load current, the settling time is less than 3.5 μs and the measured reference tracking bandwidth is about 1 MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2 μA/MHz.

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Arun Rao

National Semiconductor

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Sachin Rao

Oregon State University

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