Sachin Yadav

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

The first monolithic integration of Ge p-FETs and InAs n-FETs on silicon substrate using a sub-120 nm III-V buffer technology is reported. A common digital etch process was developed to precisely control the etching of InAs and Ge, enabling the realization of Ge p-FETs and InAs n-FETs with a body thickness Tbody of below 5 nm and channel lengths LCH smaller than 200 nm. Other process modules such as common gate stack and contact processes were also employed. By comparing with other reports that co-integrated Si1-xGex p-FETs and InxGa1-xAs n-FETs on Si or Ge substrates, the Ge p-FETs and InAs n-FETs in this work achieve the highest drive current ION.

Heteroepitaxial growth of In0.30Ga0.70As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

We report on the growth of an In0.30Ga0.70As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 107 cm−2 with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with IDS of 70 μA/μm and gm of above 60 μS/μm, demonstrating the high quality of the grown materials.

Monolithic Integration of InAs Quantum-Well n-MOSFETs and Ultrathin Body Ge p-MOSFETs on a Si Substrate

Integration of In_{<italic>x</italic>}Ga_{1–<italic>x</italic>}As n-MOSFETs and Si_{<italic>y</italic>}Ge_{1–<italic>y</italic>} p-MOSFETs could be a key to realize future low-power and high-speed logic circuits. In this paper, monolithic integration of InAs n-MOSFETs and Ge p-MOSFETs on a Si substrate is reported. To address the challenge of integrating materials with large lattice mismatch (InAs and Ge on Si substrate), a sub-120-nm GaSb-on-GaAs buffer on a germanium-on-insulator (GeOI) starting substrate is employed. The strain resulting from the 7.78% lattice mismatch between the GaSb and GaAs layers is mainly relaxed via interfacial misfits at the GaSb/GaAs interface, enabling significant reduction in the buffer thickness. For device fabrication, a self-aligned gate last process flow with Si-CMOS-compatible modules is used. To realize raised source-drain device architecture, a combination of dry and digital etch processes is developed to etch InAs and Ge cap layers. Devices with channel thicknesses less than 5 nm and channel lengths less than 200 nm are realized for both n- and p-MOSFETs, with promising electrical characteristics.

Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules

We report the first demonstration of a novel vertically stacked structure comprising InAs nanowires and GaSb nanowires, enabled by an extremely-thin (sub-150 nm) III-V buffer technology on a Si platform. This led to the realization of InAs n-FETs and GaSb p-FETs based on the stacked InAs or GaSb nanowires (NWs), respectively, employing multiple common modules such as gate stack and contact processes. Decent transfer characteristics with SS of 126 mV/decade and DIBL of 285 mV/V were obtained for the InAs n-FET with a channel length LCH of 20 nm. For the vertically stacked GaSb NW p-FET (LCH of 500 nm), the lowest reported SS of 188 mV/decade and highest ION/IOFF ratio of 3.5 orders were achieved for III-V p-FETs on Si substrate.

Gate-All-Around In 0.53 Ga 0.47 As Junctionless Nanowire FET With Tapered Source/Drain Structure

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length (L_CH), NW height (H_NW), and NW width (W_NW) were realized. Despite having a large equivalent oxide thickness of ~4.5 nm, high extrinsic transconductance (G_m,ext) of 820 μS/μm was achieved at V_D of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance (R_SD) of 275 Ω · μm, which is one of the lowest among the reported 3-D InGaAs MOSFETs.

The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs

The worlds first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths L<inf>ch</inf> down to 50 nm and fin width W<inf>Fin</inf> down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high G<inf>m, int</inf>, of 807 μS/um (VDs of −0.5 V), and the highest G<inf>m, int</inf>/S<inf>sat</inf>, were achieved. The highest high-field hole mobility of 208 cm2/Vs (at inversion carrier density of 8×10⁻² cm⁻²) for GeSn p-FETs with CVD grown GeSn channel was also obtained.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs)

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an ION/IOFF ratio of more than 106 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

Enabling low power and high speed OEICs: First monolithic integration of InGaAs n-FETs and lasers on Si substrate

We report the first monolithic integration of InGaAs channel transistors with lasers on a Si substrate, achieving a milestone in the direction of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers for realizing transistors and lasers were grown epitaxially on the Si substrate using MBE. InGaAs n-FETs with Ion/Ioff ratio of more than 106 and very low off-state leakage current were realized. In addition, fabrication process with a low overall processing temperature (≤ 400 °C) was used to realize electrically-pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm and a linewidth of less than 0.5 nm at room temperature.

Monolithic integration of InGaAs n-FETs and lasers on Ge substrate

We report the first monolithic integration of InGaAs channel field-effect transistors with InGaAs/GaAs multiple quantum wells (MQWs) lasers on a common platform, achieving a milestone in the path of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers used for realizing transistors and lasers were grown epitaxially on the Ge substrate using molecular beam epitaxy (MBE). A Si-CMOS compatible process was developed to realize InGaAs n-FETs with subthreshold swing SS of 93 mV/decade, ION/IOFF ratio of more than 4 orders of magnitude with very low off-state leakage current, and a peak effective mobility of more than 2000 cm2/V·s. In addition, fabrication process uses a low overall processing temperature (≤ 400 °C) to maintain the high quality of the InGaAs/GaAs MQWs for the laser. Room temperature electrically-pumped lasers with a lasing wavelength of 1.03 µm and a linewidth of less than 1.7 nm were realized.

In 0.30 Ga 0.70 As QW MOSFETs with peak mobility exceeding 3000 cm 2 /V·s fabricated on Si substrates

We report the fabrication of self-aligned In_0.30Ga_0.70As quantum well (QW) MOSFETs on Si substrates. The layer structures for device fabrication were grown using MOCVD on a 200 mm Si substrate with threading dislocation density lower than 2×10⁷ cm^-2. Si-CMOS compatible process modules were used. The QW MOSFET achieved a drive current exceeding 200 μA/μm at V_GS-V_TH = 1.75 V and V_DS = 1.2 V at channel length of 0.9 μm. Furthermore, peak device mobility of 3011 cm²/V·s was obtained.