Sachio Hayashi

EMI-noise analysis under ASIC design environment

Electromagnetic compatibility (EMC) has become more and more important in designing electronic systems. Although electromagnetic radiation itself mainly occurs from off-chip conductors, the ultimate noise source is in LSI chips. Among the noise distribution paths, the power-line conducting noise is the most significant source of electromagnetic interference (EMI)-noise caused by LSIs. This paper introduces an EMI-noise analysis method suitable for application-specific integrated circuit design environment especially focusing on the power-line conducting noise. Modeling method for power network and switching activity, simulation flow, and experimental results are presented. Experimental results show that our modeling methodology estimates capacitance values with sufficient accuracy and reproduces the relative differences in EMI-noise levels.

Full-chip analysis method of ESD protection network

With the advance of process technology, the electrostatic discharge (ESD) problem becomes more and more serious. To prevent design iterations caused by ESD failures, it is necessary to verify the ESD protection network at design stage. In this paper, we present a full-chip analysis method of the ESD protection network, which can analyze pad voltages for every pair of pads. Since the proposed method combines the merits of shortest path search and circuit simulation, it can analyze pad voltages more accurately than shortest path search, with a little overhead of run time. The experimental results show that the proposed method can predict the reduction effect of pad voltage by ESD remedies. And it is shown that for a chip with 858 pads, the proposed method can analyze pad voltages of every pair of pads within 2 hours.