Takuma Aoyama
Toshiba
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Publication
Featured researches published by Takuma Aoyama.
international solid-state circuits conference | 2014
Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Kenichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; Atsushi Kunimatsu; Yukihito Oowaki
Mobile devices have made remarkable advances in recent years. They generally use embedded NAND storage devices, which are tiny (10s of millimeters square) and low-power (around 1W in the active state) single BGA packages that contain both a controller and NAND chips. Figure 19.3.1 shows read performance of recent embedded NAND storage device products and the maximum link speeds in their standards. The figure indicates that more powerful embedded NAND storage devices are desired by the market. In particular, universal Flash storage (UFS) 2.0, the latest standard, defines high link speed, which is 3× faster than the recent embedded multimedia card (eMMC). In this context, we develop a UFS 2.0 device that introduces new features to the conventional embedded NAND storage device controller architecture to improve read performance. Figure 19.3.2 shows a block diagram of our controller. We improve the read performance in the following ways: 1) suppress the number of NAND read accesses and reduce the read latency by introducing unified memory (UM) and caching data for address translations on it, 2) increase the number of NAND chips activated simultaneously with dedicated hardware and new command scheduling, and 3) maximize bandwidth by supporting 5.8Gb/s 2-lane M-PHY link with low-power analog circuits.
asian solid state circuits conference | 2014
Kenta Yasufuku; Naoto Oshiyama; Toshitada Saito; Yukimasa Miyamoto; Yutaka Nakamura; Ryota Terauchi; Atsushi Kondo; Takuma Aoyama; Masafumi Takahashi; Yukihito Oowaki; Ryoichi Bandai
This paper presents a UHS-II SD card controller with 240MB/s write and 260MB/s read throughput. Two opposite direction IO lanes for down- and up-streams are quickly switched as single direction for double data rate, without adding extra IO pins. The proposed clock data recovery (CDR) logic can detect symbols within 20ns and minimizes this lane switching overhead. The developed SLVS-type driver that can reduce the common to differential return loss by 15dB is also introduced to improve the noise tolerance.
Archive | 1994
Takuma Aoyama; Akira Takiba
Archive | 2008
Mikio Shiraishi; Takuma Aoyama
Archive | 2010
Tomoyuki Yoda; Takuma Aoyama; Sachio Hayashi
Archive | 2012
Satoshi Kameda; Takuma Aoyama
Archive | 2012
Nobutaka Kitagawa; Takuma Aoyama; Yoshitaka Sampei
Archive | 2010
Takuma Aoyama; Sachio Hayashi; Tomoyuki Yoda; 左千夫 林
Archive | 2015
Shinsuke Fujii; Takuma Aoyama; Hiroyuki Shibayama
Archive | 2014
Yusuke Tsurui; Ryota Terauchi; Takuma Aoyama