Sadahiro Tani

A layout system for the random logic portion of MOS LSI

The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on the basis of a set of optimization heuristics. Experimental results of the layout system are also shown so as to reveal that the random logic portion can be realized in much the same area as can be done by manual layout.

An offset distribution modification technique of stochastic flash ADC

A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator inputreferred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.

Parasitic capacitance modeling for multilevel interconnects

The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be represented by a simple expression adjusted to the results computed by an electromagnetic field solver based on a two-dimensional capacitance model. An approximate expression of the total capacitance between two crossing interconnects is obtained by summing the capacitances in all regions. In order to evaluate the accuracy of this approximation, the capacitance calculated by the attained expression is compared with the one obtained by a three-dimensional field solver, and it turns out that the error is less than 5%.

An analog front-end employing 87 dB SNDR stochastic SAR-ADC for a biomedical sensor

The present paper introduces a novel ADC for biomedical sensors that embeds successive-approximation-register ADC and stochastic flash ADC operations. The ADC in the analog-front-end IC fabricated in a 130-nm CMOS process demonstrated 87 dB SNDR for a 20.5 Hz input signal at an oversampling rate of 250 kS/s with calibration by a supervised machine learning technique.

Interconnect capacitance extraction for system LCD circuits

This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI interconnects. We focus on a pattern matching method with interpolation to implement an accurate and efficient capacitance extraction system, and present good implementations that are suitable for system LCD circuits. To reduce computational cost, interconnect structures are spatially divided into several sub-regions considering capacitance coupling range, and analyzed in each sub-region using a capacitance database pre-characterized by a 3-D field solver. This paper evaluates tradeoff curves between characterization cost and extraction accuracy for four division methods in lattice structures that are basic and common structures in LCD driver circuits. Experimental results reveal efficient division methods for accurate capacitance extraction.

A calibration with an adaptive data selection based on Bayes estimation for a successive stochastic approximation ADC system

A novel low-power high-precision analog-to-digital converter (ADC) called the successive stochastic approximation ADC (SSA-ADC) has been recently proposed, which has two kinds of outputs from a stochastic flash ADC (SF-ADC) and a successive approximation register ADC (SAR-ADC) modes, respectively. In this paper, we propose a software-level calibration and encoding based on the machine learning for the two outputs to generate an total output. In addition, from the practical viewpoint, we propose an incremental learning which selects additional data by keeping a balance between the uniform random and preferential selections based on the Bayesian estimation at each learning.

A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION

This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or digital-assistant cancellation. Combining a conventional dynamic latched comparator with a one-stage amplifier benefits from not only an enhancement in comparator gain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by using a 130-nm CMOS process, show that the comparator achieved a 3.8 mV equivalent input-referred offset voltage at a 10 MHz clock rate while dissipating 2.7 μW from a 1.2V supply.

Parasitic capacitance modeling for TFT liquid crystal displays

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for TFT liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at intersections and parallel runs of interconnects. To derive a simple and accurate approximate expression, the interconnects in such a structure are divided into a few basic coupling regions such that with the use of a 2D model the capacitance in-each region can be calculated by an electro-magnetic field solver. The total capacitance attained by summing the capacitances of these regions proves to be approximated within a relative error of 5% as compared with that obtained by using a 3D field solver.