Shuji Tsukiyama

A New Algorithm for Generating All the Maximal Independent Sets

The problem of generating all the maximal independent sets (or maximal cliques) of a given graph is fundamental in graph theory and is also one of the most important in terms of the application of graph theory. In this paper, we present a new efficient algorithm for generating all the maximal independent sets, for which processing time and memory space are bounded by

An algorithm for single-row routing with prescribed street congestions

O(nm\mu)

A statistical static timing analysis considering correlations between delays

and

Graph based analysis of 2-D FPGA routing

O(n+m)

Double-row planar routing and permutation layout

, respectively, where n, m, and

Area-efficient drawings of rectangular duals for VLSI floor-plan

\mu

An algorithm for the via assignment problem in multilayer backboard wiring

are the numbers of vertices, edges, and maximal independent sets of a graph.

Not necessarily more switches more routability [sic.]

The single-row routing approach for layout has attracted a great deal of interest and is in a position to become one of the fundamental routing methods for high density multilayer printed wiring boards (PWBs). A specific development has recently been accomplished on this approach [12], namely: Necessary and sufficient conditions for optimum routing have been obtained. Nonetheless, there still remains a fundamental problem to be overcome, that is, to develop an algorithm to find the optimum solution. The present paper derives an alternate set of necessary and sufficient conditions for the same problem. These are easy to check and are tailored for algorithm development. An efficient algorithm in the special cases of upper and lower street congestions up to two has been proposed. These special cases are particularly of interest in the design of practical PWBs.

On computational complexity of a detailed routing problem in two dimensional FPGAs

In this paper, we present a new algorithm for the statistical static timing analysis of a CMOS combinatorial circuit, which can treat correlations of arrival times of input signals to a logic gate and correlations of switching delays in a logic gate. We model each switching delay by a normal distribution, and use a normal distribution of two stochastic variables with a coefficient of correlation for computing the distribution of output delay of a logic gate. Since the algorithm takes the correlation into account, the time complexity is O(n*m) in the worst-case, where n and m are the numbers of vertices and edges of the acyclic graph representing a given combinatorial circuit.

A New Global Router for Gate Array LSIsi

In this paper, we study the two-dimensional FPGA, Xilinx-like routing architectures and present the first known computational complexity results for them. The routing problem is formulated as a two-dimensional interval packing problem and is proved to be NP-complete with or without doglegs. Next, we consider other routing structures obtained from the industrial one by arbitrarily changing switch box connection topology while maintaining the same connection flexibility. There is an exponentially large number of such routing structures. We further prove that there does not exist a better routing architecture among the members of this large domain. In addition, we prove that there is no constant bound on the mapping ratio of a track number required by a detailed routing to a global routing channel density for the studied architectures. Finally, we show two directions of changing the routing architectures which yield polynomial time mapping solutions and constant bounded mapping ratios. Our theoretical analysis is intended to give some insight to, and understanding of this new routing problems fundamental properties.