Fouad E. Kiamilev

Grain-size considerations for optoelectronic multistage interconnection networks

This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K x K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MINs.

Potentials of two-photon based 3-D optical memories for high performance computing.

The advent of optoelectronic computers and highly parallel electronic processors has brought about a need for storage systems with enormous memory capacity and memory bandwidth. These demands cannot be met with current memory technologies (i.e., semiconductor, magnetic, or optical disk) without having the memory system completely dominate the processors in terms of the overall cost, power consumption, volume, and weight. As a solution, we propose an optical volume memory based on the two-photon effect which allows for high density and parallel access. In addition, the two-photon 3-D memory system has the advantages of having high capacity and throughput which may overcome the disadvantages of current memories.

Programmable optoelectronic multiprocessors and their comparison with symbolic substitution for digital optical computing

This paper introduces programmable arrays of optically inter-connected electronic processors and compares them with conventional symbolic substitution (SS) systems. The comparison is made on the basis of computational efficiency, speed, size, energy utilization, programmability, and fault tolerance. The small grain size and space-invariant connections of SS lead to poor computational efficiency, difficult programming, and difficult incorporation of fault tolerance. Reliance on optical gates as its fundamental building elements is shown to give poor energy utilization. Programmable optoelectronic multiprocessor (POEM) systems, on the other hand, provide the architectural flexibility for good computational efficiency, use an energy-efficient combination of technologies, and support traditional programming methodologies and fault tolerance. Although the inherent clock speed of POEM systems is slower than that of SS systems, for most problems they will provide greater computational throughput. This comparison does not take into account the recent addition of crossover interconnect and space-variant masks to the SS architecture.

Optical expert system based on matrix-algebraic formulation.

This paper describes an expert system paradigm based on matrix algebra. The knowledge base of the expert system is stored in binary matrices, while the learning and inference processes are done by matrix algebra operations. This method is highly parallel and can take full advantage of the inherent parallelism and connectivity of optics. An optoelectronic architecture that implements this system is presented. In addition, the method is compared with the sequential search methods written in the programming language PROLOG to illustrate their differences and commonalities.

Design trade-offs in optoelectronic parallel processing systems using smart-SLMs

Optoelectronic devices with free-space optical interconnections offer new possibilities in massively parallel processing. The trade-offs involved in system design and device selection for optoelectronic implementations are examined. System design trade-offs are approached from algorithmic and technological standpoints. From the algorithmic standpoint, new architectures based on expander graphs, that have been shown to provide low-contention fault-tolerant communication, are discussed. Optoelectronic systems which implement such random graphs can be folded to reduce the hardware cost or unfolded to increase bandwidth. They can also be partially folded by increasing the grain size or by reducing the randomness of the graph topology to reduce the complexity of the interconnection holograms. An optoelectronic and a VLSI implementation of a multistage interconnection network are compared from a technological standpoint. Physical design parameters, such as the chip size or the number of phase levels of the interconnection holograms, are related to the system design metrics such as bandwidth, volume, area and power. It is shown that the optoelectronic implementations have higher performance and are more cost-effective than VLSI implementations. These results are also used to provide general guidelines for device selection in the design of smart pixels/smart spatial light modulators based optoelectronic systems.

Architecture of an integrated computer-aided design system for optoelectronics

The architecture of an integrated CAD system to automate the design of optoelectronic systems is presented in this paper. Optoelectronic technology with free-space optical interconnects offers the potential to build high-performance computers. As this technology matures increased design complexity will mandate the use of CAD. CAD tools and specifications for the design process of optoelectronic systems are described. The proposed architecture extends existing CAD technologies to optoelectronics.© (1991) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Highly parallel consistent labeling algorithm suitable for optoelectronic implementation

Constraint satisfaction problems require a search through a large set of possibilities. Consistent labeling is a method by which search spaces can be drastically reduced. We present a highly parallel consistent labeling algorithm, which achieves strong k-consistency for any value k and which can include higher-order constraints. The algorithm uses vector outer product, matrix summation, and matrix intersection operations. These operations require local computation with global communication and, therefore, are well suited to a optoelectronic implementation.

Programmable opto-electronic multiprocessor systems

Programmable Opto-electronic Multiprocessor systems (POEMs) are reviewed in terms of their architecture and system implementation considerations. We compare POEMs with VLSI computers based on scalability, performance and technological feasibility. Our results show that for parallel computers requiring a large number of globally con- nected simple processing elements POEM systems out perform their VLSI counterparts. We also report on the implementation of the POEM prototype currently in progress at UCSD.

Effects of optoelectronic device characteristics on the performance and design of POEM systems

The Programmable Opto-Electronic Multiprocessor (POEM) combines free-space optical interconnects, optoelectronic devices, and electronic processors to perform computations. This paper investigates a specific POEM architecture for a multistage interconnection network application. For the chosen system, there is an optimum combination of optics and electronics. The effect of varying optoelectronic device parameters on the system performance is also examined.

Power efficient parallel optical communication links

The development of power efficient parallel optical communication links by using end-to-end power negotiation algorithm in conjunction with a robust and low latency line code is presented.