Saeideh Shirinzadeh

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs

Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing - particularly in MAJ-based realizations - and the use of techniques proposed for optimization.

An MIG-based compiler for programmable logic-in-memory architectures

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays. Our approach uses Majority-Inverter Graphs (MIGs) to manage the computational operations. In order to obtain a performance and resource efficient program, we employ optimization techniques both to the underlying MIG as well as to the compilation procedure itself. In addition, our proposed approach optimizes the program with respect to memory endurance constraints which is of particular importance for in-memory computing architectures.

Multi-Objective BDD Optimization with Evolutionary Algorithms

Binary Decision Diagrams (BDDs) are widely used in electronic design automation and formal verification. BDDs are a canonical representation of Boolean functions with respect to a variable ordering. Finding a variable ordering resulting in a small number of nodes and paths is a primary goal in BDD optimization. There are several approaches minimizing the number of nodes or paths in BDDs, but yet no method has been proposed to minimize both objectives at the same time. In this paper, BDD optimization is carried out as a bi-objective problem using two aforementioned criteria. For this purpose, we have exploited NSGA-II which has been proven to fit problems with a small number of objectives. Furthermore, the algorithm is facilitated with an objective priority scheme that allows to incorporate preference to one of the objectives. Experimental results show that our multi-objective BDD optimization algorithm has achieved a good trade-off between the number of nodes and the number of paths. Comparison of the results obtained by applying priority to the number of nodes or paths with node and path minimization techniques demonstrates that the proposed algorithm can find the minimum of the preferred objective in most cases as well as lowering the other objective simultaneously.

Multi-objective BDD optimization for RRAM based circuit design

Resistive switching property enables various promising applications such as design of non-volatile in-memory computing devices which has attracted high attention to Resistive Random Access Memories (RRAMs). In this work, we present a multi-objective BDD optimization approach for RRAM based logic circuit design. Dissimilar to classical BDD optimization, evaluating the cost metrics of the circuits in this case does not only depend on the number of BDD nodes but is more advanced. We have utilized a non-dominated sorting genetic algorithm for bi-objective BDD optimization with respect to the number of required RRAMs and computational steps addressing the area and delay of the resulting circuits, respectively. The algorithm also allows preference to one of the objectives if it is of higher significance. Experimental results show that the proposed multi-objective genetic algorithm achieves considerable reduction in both aforementioned criteria in comparison with an existing approach.

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm

Approximate computing has gained high attention in various applications that can benefit from a reduction in costs by lowering the accuracy. In this paper we present an optimization approach for functional approximation of Binary Decision Diagrams (BDDs) which are known for their widespread applications in electronic design automation and formal verification. We propose a three-objective ε-preferred evolutionary algorithm with the first objective set to the BDD size which is given higher priority to the two other objectives set to errors caused by approximation. This is highly demanded by the application to ensure that the minimum size for the approximated BDD is accessible when the error metrics meet certain threshold values. While BDD size minimization is guaranteed by incorporating priority, the use of ε in the proposed approach ensures to guide the search towards desired error values in parallel. Experiments confirm the efficiency of the proposed approach by a size improvement of 64.24% at a fair cost of 3.86% inaccuracy on average.

An adaptive prioritized ε -preferred evolutionary algorithm for approximate BDD optimization

Approximate computing is an emerging methodology that allows to increase efficiency in a range of resilient applications for an affordable loss of precision or quality. In this paper, we exploit approximation in a multi-criteria optimization approach for the widely used data structure Binary Decision Diagram (BDD) to achieve higher efficiency besides lowering the inaccuracy. For this purpose, we utilize an ε-preferred evolutionary algorithm giving a higher priority to minimize BDD sizes as well as maintaining certain error constraints. In particular, we propose an adaptive ε-setting method which adds an automated factor to the algorithm based on the behavior of the function under approximation. This improves the performances of the algorithm by correcting the effect of the user set error constraints which can restrict the dimensions of the search and can lead to immature convergence. In comparison with the non-optimized BDDs, the proposed algorithm achieves a high gain of 68.02% at a low cost of 2.12% inaccuracy for the whole benchmark set. The experimental results also reveal a considerable improvement of 25.19% in the average value of error rate besides reduction in BDD sizes compared to the manual ε-setting approach.

Endurance management for resistive Logic-In-Memory computing architectures

Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.

Logic Synthesis for Majority Based In-Memory Computing

The resistive switching property exhibited by many emerging memory technologies enables the execution of logic operations directly with memory arrays. This opens new horizons to a modern era of computer architectures beyond the traditional Von Neumann architectures which have separated memory and computing units. In this chapter, the memristive behavior of RRAM is abstracted as a majority based logic operation for efficient synthesis of logic-in-memory circuits and systems. A majority based Programmable Logic-in-Memory (PLiM) architecture is also introduced and compiled addressing the latency and area issues.

A PLiM Computer for the Internet of Things

Emerging applications are dramatically changing computer architecture requirements, with a shift toward big data that is processed using simple computations. A programmable logic-in-memory (PLiM) computer can allow memory cells to perform primitive logic operations and therefore compute without needing to communicate with a processing unit.