Arighna Deb

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits

Optical circuits are considered a promising emerging technology for applications in ultra-high-speed networks or interconnects. However, the development of (automatic) synthesis approaches for such circuits is still in its infancy. Although first generic and automatic synthesis approaches have been proposed, no clear understanding exists yet on how to keep the costs of the resulting circuits as small as possible. In the domain of optical circuits, this is particularly interesting for the number of gates and the effect of so-called splitters to the signal strength. In this work, we investigate this relation by considering a variety of (existing as well as proposed) synthesis approaches for optical circuits. Our investigations show that reducing the number of gates and reducing the number of splitters are contradictory optimization objectives. Furthermore, the performance of synthesis guided with respect to gate efficiency as well as synthesis guided with respect to splitter freeness is evaluated and an overhead factor between the contradictory metrics is experimentally determined.

A regular network of symmetric functions in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a technology which has the potential of faster speed, smaller size and minimum power consumption compared to transistor based technology. In quantum-dot cellular automata, the basic elements are simple cells. The cells are used to construct majority voter gate, inverter and wire. This paper utilizes the unique characteristics of QCA majority voter gate to realize symmetric functions. In this paper, we introduce a synthesis technique for implementing totally symmetric Boolean functions using Quantum-dot Cellular Automata (QCA) logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3-input majority voter gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. The designs are simulated and the simulation result indicates the complexity, area and delay of the proposed designs.

Reversible circuit synthesis of symmetric functions using a simple regular structure

In this paper, we introduce a new method to realize symmetric functions with reversible circuits. In contrast to earlier methods, our solution deploys a simple and regular cascade structure composed of low-cost gates which enables significant reductions with respect to quantum costs. However, the number of garbage outputs increases slightly. To overcome this, we next propose an optimized design by reusing the garbage outputs. The resulting design thus offers a powerful approach towards reversible synthesis of symmetric Boolean functions.

Reversible synthesis of symmetric boolean functions based on unate decomposition

In this paper, we introduce a new method to realize symmetric Boolean functions with reversible logic based on unate decomposition. In contrast to earlier synthesis methods, our solution uses a simpler circuit structure of reversible gates, which enables a significant reduction with respect to quantum cost. The resulting design offers an improved solution to reversible synthesis of symmetric Boolean functions.

OR-Inverter Graphs for the Synthesis of Optical Circuits

The advances in silicon photonics motivate theconsideration of optical circuits as a promising circuit technology. Recently, synthesis for this kind of circuits received significantattention. However, neither the corresponding function descriptions nor the resulting synthesis approaches explicitly consideredhow optical circuits actually conduct computations – eventuallyleading to circuits of improvable quality. In this work, we presenta synthesis flow which has explicitly been developed for thistechnology. To this end, we introduce and exploit OR-Invertergraphs (OIGs) – a data-structure which is particularly suitedfor the design of optical circuits. Experimental results confirmthe efficacy of the OIG structure and the resulting synthesisapproach. Compared to several alternative solutions – relyingon conventional function representations – the number of gatescan be reduced by half or even significantly more than that.

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability

In this article, we introduce a novel method of synthesizing symmetric Boolean functions with reversible logic gates. In contrast to earlier approaches, the proposed technique deploys a simple, regular, and cascaded structure consisting of an array of Peres and CNOT gates, which results in significant reduction with respect to the quantum cost. However, the number of circuit inputs may increase slightly when such cascades are used. In order to reduce their number, we next propose a postsynthesis optimization phase that allows judicious reuse of circuit lines. In addition to offering a cost-effective synthesis methodology, the proposed reversible logic structure supports elegant testability properties. With respect to all single or partial missing gate faults (SMGFs and PMGFs), or repeated gate faults (RGFs) in such an n-input circuit module, we show that it admits a universal test set of constant cardinality (=3) for any value of n. Thus, considering both the cost and testability issues, this approach provides a superior option for synthesizing symmetric functions compared to existing designs.

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization

New prospects in several emerging technologies such as quantum computation and certain aspects of low-power design motivated an intensive consideration of the design of reversible circuits. Since most of the existing synthesis approaches usually generate circuits of high costs, post-synthesis optimization is frequently applied. Here, the reduction of control line connections is a major focus as they are a main reason for high quantum costs in the respective reversible circuits. Previous approaches aimed for exploiting so-called common control lines for this purpose. However, while these solutions indeed lead to substantial improvements in the costs, they inherit some drawbacks and restrictions. In this work, we propose an alternative approach for the reduction of common control lines in reversible circuits, which (1) is based in the concepts of previously proposed solutions, but (2) combines them in a new fashion. This enables us to achieve the same or even better improvements, while - at the same time - overcome their drawbacks. Experimental evaluations confirm these benefits, i.e. significant improvements compared to the previous methods can often be achieved without the need to deal with their drawbacks.

Modular Design for Symmetric Functions Using Quantum Quaternary Logic

In this paper, we propose a method to realize symmetric binary functions as quaternary quantum/reversible circuits. In contrast to the existing binary synthesis methods, our design in quaternary domain offers a simple and regular cascade structure composed of quaternary quantum modules which enables significant reductions with respect to number of lines, levels and quantum costs. Further, a method to obtain an optimal realization is presented, this uses a few special quaternary quantum modules of low quantum cost. Experimental results confirm that our new method leads to realizations in quaternary domain with a significant reduction in number of lines, levels and quantum cost compared to the existing approaches in binary domain. Hence, our design in quaternary logic offers a useful alternative to existing designs in binary logic for realizing symmetric functions.

An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata

In recent years, majority-logic received significant attention as a synthesis approach for large Boolean functions. This logic is easily implemented in Quantum-dot cellular automata (QCA) technology which is emerging as an alternative to CMOS technology. In fact, majority logic gate serves as the basic logic unit in the digital design of QCA circuits. This paper introduces a synthesis technique for implementing totally symmetric Boolean functions using majority logic. First, a simple regular module is designed to synthesize unate symmetric functions. The structure uses 3-input majority gates. General symmetric Boolean functions are then realized following a unate decomposition method. We study the synthesis of some well known benchmark symmetric functions using the proposed method. Comparison with existing synthesis approaches confirms the efficacy of our method.

Synthesis of Symmetric Boolean Functions Using a Three-Stage Network

This paper introduces a new three-stage circuit structure for synthesizing symmetric Boolean functions. The first stage of the proposed method improves upon an earlier approach to the synthesis of a special class of symmetric functions, known as matriochka symmetric functions. The second stage realizes the elementary symmetric functions from the matriochka symmetric functions of the first stage. Finally, in the third stage of the design, these elementary symmetric functions are used to synthesize any arbitrary symmetric function. Experiments on several benchmark functions show a reduction in circuit area compared to earlier results.