Sagar Mukherjee

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm2 and consumes 127 μW of average power while operating with an input frequency (fin) of 5 MHZ, and a supply voltage of 1.8Volt. For this proposed architecture, the maximum sampling rate is obtained as 0.2 GSPS. At 0.2 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 20.84 dB, yielding the Effective Number of Bits (ENOB) as 3.2 bit.

Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme

Optimization of power and speed is the most crucial issue for any low-voltage, low-power design. In this paper an Energy Efficient, Robust 18 Transistor (18T) 1-bit Full Adder (FA) cell, modified with the concept of Mixed Threshold Voltage (MVT) scheme, is reported. The entire design is done in 45nm technology, and compared to the conventional one, a considerable amount of reduction in the Average Power consumption (Pavg) as well as the Power Delay Product (PDP) has been achieved. For an operating frequency of 500MHz, the Pavg is as low as 9.31×10-8 Watt, whereas the PDP for Sum output is found to be 1.115×10-18 Joule. The analyses have been carried out with help of the simulation runs on SPICE, and that indicate, for the lower Supply Voltages (Vdd), MVT scheme can be a more practical option than the simple dual threshold technique.

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET

In this work, the effect of lateral straggle on independently driven underlap double gate MOSFET (IDUDGMOS) is presented based on analog and digital circuit performances. The lateral straggle in IDUDGMOS devices is due to process induced source/drain out diffusion and it varies the desired device characteristics. For the analysis of this variation on circuit performance of the device, an Amplitude Modulator (AM) circuit and a SRAM circuit is considered for analog and digital circuit application considerations respectively. For the analysis of the device in AM circuit the parameters studied are the bandwidth, the gain and the linearity, correspondingly for SRAM circuit the parameters studied are the Static Noise Margin (SNM) and the circuit delay. The analysis of the AM circuit designed using the IDUDGMOS suggested that the power loss and the bandwidth of the circuit degrade with increasing lateral straggle. For the SRAM circuit the analysis suggests that larger straggle lengths in the device results in reduced time delay but, the SNM is smaller as well.

Implementation of the Cluster based Tunable Sleep Transistor Cell Power Gating Technique for a 4×4 Multiplier Circuit

A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4x4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4x4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638x10-5 Watt of Average Power while being operated with the nominal case of the bit configuration word, that is, 1000.

Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance

In this study, the analogue performance of radio-frequency (RF) range amplifiers and ring oscillators designed using fully depleted silicon on insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied for different back oxide (BOX) thickness. The analysis exemplifies the need for BOX thickness variation analysis for the superior analogue/RF performance. The analogue parameters of the circuit analysed for different BOX thickness are the bandwidth, the linearity and the power consumption. The study shows that for an FDSOI MOSFET-based amplifier circuit, with increasing BOX thickness the bandwidth increases and the gain decreases. Also an optimum value of gain–bandwidth product for the amplifier is proposed considering the BOX thickness and the gate length of the device. It is also shown that frequency of oscillation for the ring oscillators increases with increasing BOX thickness.

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET

In this brief, a novel programmable low power analog-to-digital converter (ADC) circuit design is proposed using independently driven underlap double gate MOSFET (IDUDGMOS) to operate in radio frequency domain and its performance is studied. The primary motivation of the design is to eliminate the need for a resistor ladder for reference voltage selection and to minimize the number of transistor used in the flash ADCs. The proposed design utilizes the back gate voltage controllability of IDUDGMOS for varying reference voltage of the comparators in the ADCs. The parameters of the designed ADC analyzed are the bandwidth, the linearity, and the power consumption of the circuit. The proposed circuit offers wider bandwidth and lower power consumption compared to earlier ADC designs.

Low-power amplitude modulator for wireless application using underlap double-gate metal–oxide–semiconductor field-effect transistor

In this study, a design guideline for a modified low-power wideband on-chip amplitude modulator (AM) based on independently driven double-gate metal–oxide–semiconductor field-effect transistor (IDDGMOS) is proposed. The AM performance is then analysed for three different types of underlap engineered IDDGMOS devices. It is observed that the modulator designed with IDDGMOS presents a higher gain and bandwidth for lower power input signals. For analysing the gain–bandwidth performance of the modulator circuit, a small signal model for the devices is considered. The linearity and noise performance of the modulator circuit for different IDDGMOS structures is analysed by studying the 1 dB compression point and the signal-to-noise ratio. The analysis suggested that the most efficient AM circuit performance is achieved for the symmetric underlap IDDGMOS device. The symmetric underlap IDDGMOS AM circuit yields a gain of 11 dB, a bandwidth of 5.5 GHz and a 47.2% efficiency with a distortion less input signal power range of −60 to −33.5 dB. Moreover, the reduced power loss is about 0.047% of the power loss obtained for the conventional complementary metal–oxide–semiconductor device, whereas the bandwidth of the circuit almost triplicates.