Sai-Wang Tam

CMP network-on-chip overlaid with multi-band RF-interconnect

In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

A scalable micro wireless interconnect structure for CMPs

This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds to thousands of cores in chip multiprocessors (CMPs), where current interconnect technologies face severe scaling limitations in excessive latency, long wiring, and complex layout. We propose a recursive wireless interconnect structure called the WCube that features a single transmit antenna and multiple receive antennas at each micro wireless router and offers scalable performance in terms of latency and connectivity. We show the feasibility to build miniature on-chip antennas, and simple transmitters and receivers that operate at 100-500 GHz sub-terahertz frequency bands. We also devise new two-tier wormhole based routing algorithms that are deadlock free and ensure a minimum-latency route on a 1000-core on-chip interconnect network. Our simulations show that our protocol suite can reduce the observed latency by 20% to 45%, and consumes power that is comparable to or less than current 2-D wired mesh designs.

Power reduction of CMP communication networks via RF-interconnects

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF-I.

RF interconnects for communications on-chip

In this paper, we propose a new way of implementing on-chip global interconnect that would meet stringent challenges of core-to-core communications in latency, data rate, and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitation of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I) through on-chip differential transmission lines. The physical implementation of RF-I and its projected performance versus overhead as the function of CMOS technology scaling are discussed as well

Millimeter-wave CMOS digital controlled artificial dielectric differential mode transmission lines for reconfigurable ICs

Digital control of the effective dielectric constant of a differential mode transmission line is shown up to 60GHz in standard CMOS technology. The effective dielectric constant is shown to increase from 5 to over 50 for the fixed artificial dielectric case. The digital controlled artificial dielectric transmission line (DiCAD) uses MOS switches to dynamically control the phase. DiCAD achieves 50% of the physically available tuning range with effective dielectric constants varying between 7 and 28. Measured results favorably agree with full-wave electromagnetic simulations.

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm2 and 0.06 mm2 die area, respectively. The dual-band transceiver achieves error-free operation (BER <; 10-15 ) with 223- 1 PRBS at 8.4 Gb/s over a distance of 10 cm.

A Dual-Band Millimeter-Wave CMOS Oscillator With Left-Handed Resonator

A new technique using a left-handed (LH) resonator to generate a multiband millimeter-wave carrier signal is proposed in this paper. The LH resonator exhibits nonlinear dispersion characteristic, which enables uneven spacing between resonant frequencies. With N stages of the LH unit cell, there are N/2 +1 resonant frequencies from the nonlinear dispersion curve. Moreover, the band selection switches are not located in the signal path, which can, therefore, dramatically reduce the size of switches and improve the overall quality factor of the resonator. A dual-band millimeter-wave oscillator in digital 90-nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3 and 55.3 GHz, respectively, with a total power consumption of 14 mW.

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput

The steep growth of digital-content consumption and increasing reliance on wireless networks has resulted in emerging standards such as IEEE 802.11ac. By employing spatial diversity, Multi-user MIMO and high-density modulation (up to 256-QAM), 802.11ac MIMO radios can provide significantly increased throughput, link robustness, and range while maintaining backward-compatibilities with existing 802.11a/n WLAN [1]. However, wide signal bandwidth and high-density modulation lead to significant challenges in all aspects of RF transceiver design, compared to previous WLAN standards. This paper introduces a fully integrated 3-stream MIMO WLAN SoC that integrates all of the functions of an 802.11a/b/g/n/ac WLAN with a record over-the-air TCP/IP throughput of 1.1Gb/s. The 40nm CMOS SoC integrates dual-band (2.4GHz and 5GHz) RF transceivers, data converters, digital physical layer, media access controller, and a PCI Express Gen-2 interface. The RF transceiver employs an all-digital fractional-N PLL with a record Figure-of-Merit (FoM) of -244dB, a wideband low-impedance bias circuit that minimizes pre-PA driver memory effect for 80MHz signal bandwidth, a dual-band receiver with 3dB/4.3dB NF, and a 5th-order Chebyshev low-pass filter with constant-Gm bias and pre-distorted filter coefficients to support up to 80MHz signal bandwidth.

Simultaneous sub-harmonic injection-locked mm-wave frequency generators for multi-band communications in CMOS

A technique for generating multiple mm-wave carrier frequencies is introduced, using simultaneous sub-harmonic injection locking of multiple VCOs to a single reference frequency. A prototype of 30 GHz and 50 GHz sub-harmonic injection-locked VCOs is realized in a 90 nm digital CMOS process and able to lock from 2nd to 8th harmonic of the reference frequency with locking range reaching 5.6 GHz. Simultaneous locking to the 3rd and 5th harmonics of a 10 GHz reference signal is also demonstrated.

A dual band mm-wave CMOS oscillator with left-handed resonator

A new technique using left-handed resonator to generate multi-band mm-wave carrier signal is proposed in this paper. The left-handed resonator exhibits non-linear dispersion characteristic which enables uneven spacing between resonant frequencies. A dual band mm-wave oscillator in 90nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3GHz and 55.3GHz respectively with a total power consumption of 14mW.