Yanghyo Kim

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm2 and 0.06 mm2 die area, respectively. The dual-band transceiver achieves error-free operation (BER <; 10-15 ) with 223- 1 PRBS at 8.4 Gb/s over a distance of 10 cm.

A Dual-Band Millimeter-Wave CMOS Oscillator With Left-Handed Resonator

A new technique using a left-handed (LH) resonator to generate a multiband millimeter-wave carrier signal is proposed in this paper. The LH resonator exhibits nonlinear dispersion characteristic, which enables uneven spacing between resonant frequencies. With N stages of the LH unit cell, there are N/2 +1 resonant frequencies from the nonlinear dispersion curve. Moreover, the band selection switches are not located in the signal path, which can, therefore, dramatically reduce the size of switches and improve the overall quality factor of the resonator. A dual-band millimeter-wave oscillator in digital 90-nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3 and 55.3 GHz, respectively, with a total power consumption of 14 mW.

High-Speed mm-Wave Data-Link Based on Hollow Plastic Cable and CMOS Transceiver

A multi-Giga-bit/s (up to 6 Gbps) and energy-efficient (1 pJ/bit/m) data link is formed by using hollow plastic cable and CMOS transceivers for short distance (8 m) digital communications. The demonstrated link couples/de-couples 60 GHz carried digital signals with roughly 6 dB loss per coupling into/from a hollow plastic cable made of relatively low-loss (~1.5 dB/m) Teflon, which is widely used for various home appliances. The CMOS transceivers are designed and implemented in 65 nm Foundry CMOS to support the intended 60 GHz operation with 28 mW power consumption under a 1 V supply.

A dual band mm-wave CMOS oscillator with left-handed resonator

A new technique using left-handed resonator to generate multi-band mm-wave carrier signal is proposed in this paper. The left-handed resonator exhibits non-linear dispersion characteristic which enables uneven spacing between resonant frequencies. A dual band mm-wave oscillator in 90nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3GHz and 55.3GHz respectively with a total power consumption of 14mW.

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface

This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace. With differential current-mode signaling, the transceiver consumes only 5.4 mW and takes only 80×100 μm2. A real-time flexible BER testing platform is established to prove that the BER of the transceiver is less than 1012.

Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface

A noncoherent amplitude shift keying (ASK)-based RF-interconnect (RF-I) system design for off-chip communication is analyzed. The proposed RF-I system exploits the simple architecture and characteristics of noncoherent ASK modulation. This provides an efficient way of increasing interconnect bandwidth by transmitting an RF-modulated data stream simultaneously with a conventional baseband counterpart over a shared off-chip transmission line. Both analysis and tested results prove that the performance of the proposed dual-band (RF+baseband) interconnect system is not limited by thermal noise interference. Therefore, a more sophisticated modulation scheme and/or coherent receiving scheme becomes unnecessary within the scope of system requirements. In addition, it confirms that the proposed inductive coupling network is able to support simultaneous bidirectional communications without using complicated replica circuits or additional filters to isolate simultaneous baseband and RF-band data streams.

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

\mu \text{W}

A

/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.

D

The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory interfaces with single-wire signaling operate at 5Gb/s/pin [1] and 6Gb/s/pin [2] with the power efficiency of 17.4pJ/b/pin and 15.8pJ/b/pin, respectively. Mobile DDR memory I/O with differential signaling has better power efficiency of 6.4pJ/b/pin [3], and so does the prior dual-band interconnect (DBI) [4] with the efficiency of 5pJ/b/pin at 4.2Gb/s/pin for simultaneous bidirectional (SBD) mobile memory I/O interface. However, DBIs differential signaling is incompatible with existing standards, and it also occupies large die area for using differential transmission lines and an LC-oscillator for generating RF-carrier. To alleviate these concerns, we propose to use a Single-Transmission-Line DBI (STL-DBI) with the best figure-of-merit (FoM) defined as data rate per pin divided by the I/O-interface die area and power consumption.