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Dive into the research topics where Ching-Te K. Chuang is active.

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Featured researches published by Ching-Te K. Chuang.


Volume! | 2004

Simulation of Nano-Scale Multi-Fingered PD/SOI MOSFETs Using the Boltzmann Transport Equation

José A. Pascual-Gutiérrez; Jayathi Y. Murthy; R. Viskanta; Rajiv V. Joshi; Ching-Te K. Chuang

This work uses a gray, a semi-gray, and a non-gray model based on the Boltzmann Transport Equation (BTE) in the relaxation time approximation to compute the temperature distribution in a nano-scale multi-finger, PD/SOI nMOSFET with copper interconnects. The BTE models were successfully incorporated in CFD software, Fluent 6.1. The BTE is used in the device layer, whereas in other regions of the device, such as the silicon substrate, buried oxide, gate oxide, poly-gate, and metal interconnects, the Fourier heat conduction equation is employed. The BTE is coupled with the heat conduction equation at the interfaces using the diffuse mismatch model (DMM). Heat dissipation in the channel region of the FET and in the metal lines of the device is specified based on circuit simulations for a clock buffer used in a microprocessor. The computed results for the temperature distribution in the multi-finger NFET using the different approaches are compared with simulations that employ the classical heat conduction equation in the entire domain. The comparisons demonstrate that the broad temperature fields in the transistor are primarily determined by the overall thermal resistances due to the various device structures; channel temperature, however, is determined in large part by sub-continuum effects. The need for direct measurements of channel temperature rather indirect gate temperature measurements is pointed out as well.Copyright


Archive | 2002

Sense-amp based adder with source follower evaluation tree

Jae-Joon Kim; Ching-Te K. Chuang; Rajiv V. Joshi; Kaushik Roy


Archive | 2008

CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT

Ching-Te K. Chuang; Jae-Joon Kim; Tae-Hyoung Kim; Pong-Fei Lu; Saibal Mukhopadhyay; Rahul M. Rao; Shao-yi Wang


Archive | 2002

Reduced integrated circuit chip leakage and method of reducing leakage

Ching-Te K. Chuang; Rajiv V. Joshi; Michael G. Rosenfield


Archive | 2003

Method of reducing leakage current in sub one volt SOI circuits

Richard B. Brown; Ching-Te K. Chuang; Peter W. Cook; Koushik K. Das; Rajiv V. Joshi


Archive | 2012

ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACCESS TRANSISTORS AND DESIGN STRUCTURE FOR SAME

Aditya Bansal; Ching-Te K. Chuang; Jae-Joon Kim; Shih-Hsien Lo; Rahul M. Rao


Archive | 2007

Apparatus and method for determining the slew rate of a signal produced by an integrated circuit

Ching-Te K. Chuang; Amlan Ghosh; Jae-Joon Kim; Rahul M. Rao


Archive | 2007

CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS

Ching-Te K. Chuang; Jae-Joon Kim; Saibal Mukhopadhyay


Archive | 2008

Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields

Ching-Te K. Chuang; Fook-Luen Heng; Rouwaida Kanj; Keunwoo Kim; Jin-Fuw Lee; Saibal Mukhopadhyay; Sani R. Nassif; Rama Nand Singh


Archive | 2002

Sense-amp based adder with source follower pass gate evaluation tree

Jae-Joon Kim; Ching-Te K. Chuang; Rajiv V. Joshi; Kaushik Roy

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