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Dive into the research topics where Sailesh Chittipeddi is active.

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Featured researches published by Sailesh Chittipeddi.


Journal of Electronic Materials | 1993

Effect of rapid thermally nitrided titanium films contacting silicided and nonsilicided junctions

Sailesh Chittipeddi; C. M. Dziuba; V. C. Kannan; M. J. Kelly; William Thomas Cochran; B. Rambabu

The effect of rapid thermally nitrided titanium films contacting silicided (titanium disilicided) and nonsilicided junctions has been studied in the temperature range of 800 to 900°C. The rapid thermal nitridation of titanium films used as diffusion barriers between aluminum and silicon, has a major impact on shallow junction complementary metal oxide semiconductor technologies. During the process of rapid thermal nitridation, the dopants in the junctions undergo a redistribution and affect the electrical properties of shallow junction structures. This work focuses on using novel contact resistance structures to measure the variation in electrical parameters for rapid thermally nitrided titanium films annealed at different temperatures. The self-aligned silicide (salicide) junctions in this study were formed using rapid thermally annealed titanium films. Electrical contact resistance testers were used to measure the interface contact resistance between the salicide and silicon, as well as between the metal and the salicide. The results show that the interface contact resistance to the p− diffused salicided junctions increases with rapid thermal nitridation of the additional titanium film, whereas the interface contact resistance to the n− diffused salicided junction shows a decrease. Further, as a function of the rapid thermal annealing temperature (for fixed titanium thickness), the nonsalicided diffusions show an increase in the interface contact resistance. The boron profiles at the TiSi2/Si interface obtained using secondary ion mass spectroscopy show an excellent qualitative agreement with the electrical results for each of the conditions discussed. The films were also characterized using Rutherford back-scattering spectrometry and transmission electron microscopy and the results show good agreement with the measured variation in electrical parameters. These results also show that as the anneal temperature is increased, the TiN thickness increases, further the change in the silicide/silicon interface position with the nitridation of the additional titanium layer was verified.


international ieee vlsi multilevel interconnection conference | 1991

The flow characteristics of borophosphosilicate (TEOS based) glass

Sailesh Chittipeddi; A.N. Velaga; A.K. Nanda; William Thomas Cochran; R.N. Graver

The authors examine the role of boron and phosphorus concentrations in the flow characteristics of borophosphosilicate (TEOS based) glass. The glass was deposited using TEOS (tetraethylorthosilicate), phosphine and TMB (trimethylborate), as precursors. Previous studies on the flow characteristics have relied on scanning electron microscopy (SEM) work to study the flow. In this work, however, the authors present a quantitative study of flow as measured using electrical flow testers which measured the metal resistance ratios over topography to those over flat for polysilicon spacings from 0.4 mu to 4.0 mu . They have studied the effect of boron and phosphorus concentrations in the regime of 3.5%-4.4% as measured using FTIR. It is found that the boron concentration is more dominant in determining the flow characteristics than the phosphorus concentrations. Further, it has also been found that the duration of the flow especially at the lower concentrations of boron (<4.0%) is important in determining the glass flow. SEM work is also presented in this study to augment the electrical data.<<ETX>>


Semiconductor Science and Technology | 1993

Effect of dopants on the thermal processing of salicided (titanium disilicided) CMOS structures

Sailesh Chittipeddi; M. J. Kelly; A N Velaga; V. C. Kannan; C. M. Dziuba; William Thomas Cochran; B Rambabu

The effect of thermal processing on salicided (self-aligned TiSi2) CMOS structures with phosphorus-doped gates has been investigated in the temperature range of 800-1000 degrees C. The salicided layer in the submicrometre structures reported in this paper was formed by rapid thermal processing of the titanium film on doped substrates in a nitrogen ambient. The interface contact resistance as a function of temperature (i.e. TiSi2/Si contact resistance) increases for both n-(As) and p-(BF2) implanted junctions, the increase is greater for the case of p (BF2) junctions. The sheet resistances measured on Van der Pauw patterns (large area) are affected by annealing temperature, time and dopant species, in addition to the substrate microstructure. The BF2-implanted phosphorus-doped polysilicon shows the maximum increase in sheet resistance on Van der Pauw patterns with thermal processing, as compared with any other case. The narrower (1.0 mu m) runners of polysilicon show greater increase in sheet resistances on thermal processing than do large-area Van der Pauw patterns.


Archive | 1991

Silicide formation on polysilicon

Sailesh Chittipeddi; Pradip Kumar Roy; Ankineedu Velaga


Archive | 1991

Method of fabricating an integrated circuit interconnection

Sailesh Chittipeddi; M. J. Kelly


MRS Proceedings | 1990

Characterization of a Rapid Thermal Annealed TiN x O y /TiSi 2 Barrier Layer

Sailesh Chittipeddi; M. J. Kelly; Charles M. Dziuba; A. S. Oates; William Thomas Cochran


MRS Proceedings | 1992

The Effect of Polysilicon Doping (Using Ion Implantation or PBr 3 Diffusion or Insitu Doping) on TiSi 2 Formation

Sailesh Chittipeddi; C. M. Dziuba; M. J. Kelly; V. C. Kannan; R. B. Irwin; P. M. Kahora; William Thomas Cochran


Archive | 2002

Cmos vertically replaced gate (vrg) transistor

Sailesh Chittipeddi; M. J. Kelly; チッティぺッディ サイレッシュ; ジェームス ケリー マイケル


Archive | 1992

IMPROVED METHOD FOR FORMING SILICIDE ONTO POLYSILICON

Sailesh Chittipeddi; Pradip Kumar Roy; Ankineedu Velaga; ヴェラガ アンキニーデュ; チッティペッディ サレー; クマー ロイ プラディップ


Archive | 2007

Integrated circuit comprising esd circuit for multi-chip module and its method

Sailesh Chittipeddi; William Thomas Cochran; Sumooha Ifuda; スモーハ イフダ; トーマス コチラン ウィリアム; チッティぺッディ サイレッシュ

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