Sajad A. Loan

A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study

A novel partial-ground-plane (PGP)-based MOSFET on a selective buried oxide (SELBOX), named PGP-SELBOX, is proposed. An extensive simulation study and the comparative analysis of the key characteristics of the PGP-SELBOX, the SELBOX, and the conventional silicon-on-insulator (SOI) devices has been performed using the 2-D device simulator Medici. The simulations have revealed that the PGP-SELBOX and the SELBOX structures are more thermally efficient than the conventional SOI device. Further, the magnitude of the short-channel effects (SCEs) is lower in the PGP-SELBOX in comparison to the SELBOX device. Though the SCE suppression is best in the thin-film SOI device, the PGP-SELBOX shows better improvement in SCE suppression in comparison to the SELBOX device. The suppression of self-heating effects and SCEs in the PGP-SELBOX results in a significant reduction in leakage current. An improved performance in terms of I ON/I OFF ratio is obtained in the PGP-SELBOX device. Further, the fT values of the PGP-SELBOX are comparable to those of the SELBOX and the SOI devices. A process flow in which a low-dose separation by implantation of oxygen technique can be employed for the fabrication of the PGP-SELBOX is also proposed.

A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current (ION) and ION/IOFF have increased by 225 and 65×, respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency (fT) in the proposed SE-SB-MOSFET (~200 GHz) has increased by 200× as compared with the conventional SB-MOSFET (~1 GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay (65×) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.

A high performance charge plasma PN-Schottky collector transistor on silicon-on-insulator

In this paper, we propose a new high performance PN-Schottky collector (PN-SC) lateral bipolar junction transistor (BJT) on silicon-on-insulator (SOI). The proposed device addresses the problem of poor speed of conventional lateral PNP-BJT device by using a Schottky collector. Further, it does not use the conventional ways of ion implantation/diffusion to realize n and p type doped region. However, it uses metal electrodes of different work functions to create n and p type charge plasma in an undoped silicon film. The simulation study of the proposed lateral PN-SC bipolar charge plasma transistor on SOI (PN-SC-BCPT) device has shown a significant improvement in current gain (?), cutoff frequency (f T) and switching performance in comparison to conventional PNP-BJT and PNP-bipolar charge plasma transistor (PNP-BCPT) devices. A significantly high ? is obtained in the proposed PN-SC-BCPT (?2100) in comparison to PNP-BCPT (?1450) and the conventional BJT (?9) devices, respectively. It has been observed that there is 89.56% and 153.5% increase in f T for the proposed PN-SC-BCPT device (2.18 GHz) in comparison to conventional PNP-BJT (1.15 GHz) and PNP-BCPT (0.86 GHz) devices, respectively. Further, reductions of 24.6% and 15.4% in switching ON-delay and 66% and 30.76% in switching OFF-delay have been achieved in the proposed device based inverters in comparison to PNP-BCPT and the conventional BJT devices based inverters, respectively. Furthermore, the proposed device does not face doping related issues and the requirement of high temperature processing is absent.

A novel high breakdown voltage lateral bipolar transistor on SOI with multizone doping and multistep oxide

A novel high breakdown voltage lateral bipolar junction transistor (LBJT) on silicon-on- insulator (SOI) is proposed. The novelty of the device is the use of the combination of multistep-doped drift region and multistep buried oxide. The steps in doping and in oxide thickness have been used as a replacement for much complex linearly varying drift doping and linearly varying oxide thickness. The LBJT structure incorporating the combination of multistep doping and multistep oxide is analyzed for electrical characteristics using a two-dimensional numerical simulator MEDICI. Numerical simulation has demonstrated that the breakdown voltage of the proposed device with a two-zone step doped (TZSD) drift region is >150% higher than the conventional device. It has been observed that increasing the number of doping zones to 3 from 2 results in a >40% rise in breakdown voltage. The proposed device gives high breakdown voltage even at high doping concentration in the collector drift region. This reduces the on-resistance of the device and thus improves its speed. The dependence of breakdown voltage on various device parameters has been extensively studied to achieve optimum device performance. A process flow for the device fabrication is also being proposed.

VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review

A contributory paper on the study of VLSI architectures of various fuzzy processors and controllers designed for various applications is presented. The paper focuses on the study of VLSI implementation of fuzzy logic hardware to result in small silicon area, high speed of operation and adaptability to different application domains. This paper reviews the circuit and architecture level designing of various components of the fuzzy processors, such as, fuzzifiers, defuzzifiers, inference and rule base. A comparative analysis of the performance of these components has been performed. It is observed that there is a scope for further improvement in terms of power consumption, speed of operation, area and redundancy in these fuzzy processors. Further, from the study it is seen that the design emphasis should be more on inference engine performance and defuzzification units, because of the complexity of computations handled by them. The optimization in these units results in a significant improvement in the overall performance of the system.

A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree MD between the fuzzified input and the antecedent membership functions MF has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MFs, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.

Architectural design of fuzzy inference processor using triangular-shaped membership function

The hardware design of a fuzzy processor is always intended to improve its inference performance for real time applications or to reduce the overall cost. The applications of fuzzy logic in various fields have always suffered from a major problem of low speed of operation. The calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture for calculating the matching between two triangular-shaped membership functions has been proposed. The VHDL implementation of the proposed architecture has been performed. The proposed architecture is more efficient in area and the speed of operation in comparison to a more complex architecture used for the trapezoid-shaped membership function. The proposed architecture has been implemented in a Xilinx Field Programmable Gate Array (FPGA). Further, from the proposed architecture, matching of other type of membership functions can also be obtained easily.

Design and Comparative Analysis of High Performance Carbon Nanotube-Based Operational Transconductance Amplifiers

In this paper, novel carbon nanotube (CNT) based operational transconductance amplifiers (OTAs) have been designed and simulated. Three types of CNT-based OTAs have been designed at 45 nm technology node and have been compared with the conventional CMOS-based OTA. The comparative analysis of the key characteristics of all the devices has revealed that a significant improvement in performance is observed in the CNT-based OTAs, particularly in a pure CNT-OTA. In the pure CNT-OTA, DC gain has increased by 218%, slew rate has increased by 22.58%, the output resistance has increased by 55.2% and the power consumption is ∼ 193 times less in comparison to the conventional CMOS-OTA. Further, common mode rejection ratio (CMRR) and power supply rejection ratio positive (PSRR+) has increased by 31.87% and 136.3%, respectively in pure CNT-OTA. The performance of CNT-based OTAs has also been studied thoroughly by varying the number of CNTs (N), CNT pitch (S) and the diameter of CNTs (DCNT) at 0.9 V. It has been observed that their performance can be improved further by using optimized values of CNT number; inter CNT-pitch and diameter. The stability analysis has shown that the pure CNT-OTA is highly stable. A 16.7% and 4% increase in phase and gain margins is achieved in the pure CNT-OTA in comparison to the bulk CMOS OTA. Finally, band and high pass filters have been realized by using the proposed CNT-based OTAs.

A novel fuzzy inference processor using trapezoidal-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree between the fuzzified input and the antecedent membership function needs a special attention of researchers, as the calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a max-min circuit, used for calculating the matching degree between two trapezoidal-shaped membership functions has been proposed. The VHDL modeling of the proposed architecture has been performed. It has been observed that the proposed architecture is area and speed efficient in comparison to an earlier architecture using trapezoid-membership function. A 33% reduction in the number of subtractors has been obtained in the proposed architecture. The architecture has been finally implemented in the XILINX FPGA.

Hybrid AlGaN/GaN high-electron mobility transistor: design and simulation

In this study, the authors propose a novel structure of high-electron mobility transistor (HEMT) with significantly improved performance. The novelty of the proposed HEMT is the realisation of two parallel induced electron layers under the source and drain electrode, one in the form of two-dimensional (2D) electron gas (2DEG) and the other in the form of charge plasma electron gas (CPEG). The proposed device is a hetrostructure GaN/AlGaN device, therefore, a 2DEG gets created. However, two metal electrodes at the source and drain terminals are used in the proposed device, which induce CPEG in an undoped AlGaN film under the source and drain electrode. Therefore, the proposed HEMT device is hybrid and has a combination of CPEG and the 2DEG. A two-dimensional (2D) calibrated simulation study of the proposed device has revealed that its hybrid nature has improved its performance significantly in comparison to the conventional HEMT device having 2DEG only. It has been observed that the ON current has enhanced by 115%, transconductance ( g m ) by 168%, cutoff frequency ( f T ) by 71% and maximum oscillation frequency ( f max ) by 65% in comparison to the conventional HEMT.