Asim M. Murshid

VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review

A contributory paper on the study of VLSI architectures of various fuzzy processors and controllers designed for various applications is presented. The paper focuses on the study of VLSI implementation of fuzzy logic hardware to result in small silicon area, high speed of operation and adaptability to different application domains. This paper reviews the circuit and architecture level designing of various components of the fuzzy processors, such as, fuzzifiers, defuzzifiers, inference and rule base. A comparative analysis of the performance of these components has been performed. It is observed that there is a scope for further improvement in terms of power consumption, speed of operation, area and redundancy in these fuzzy processors. Further, from the study it is seen that the design emphasis should be more on inference engine performance and defuzzification units, because of the complexity of computations handled by them. The optimization in these units results in a significant improvement in the overall performance of the system.

A novel fuzzy inference processor using trapezoidal-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree between the fuzzified input and the antecedent membership function needs a special attention of researchers, as the calculation of matching degree always needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a max-min circuit, used for calculating the matching degree between two trapezoidal-shaped membership functions has been proposed. The VHDL modeling of the proposed architecture has been performed. It has been observed that the proposed architecture is area and speed efficient in comparison to an earlier architecture using trapezoid-membership function. A 33% reduction in the number of subtractors has been obtained in the proposed architecture. The architecture has been finally implemented in the XILINX FPGA.

Carbon Nanotube Based Operational Transconductance Amplifier: A Simulation Study

MOS technology is convenient for implementing OTAs because MOSFETs are inherently voltage-controlled current devices. A variety of CMOS OTAs with different topologies have been developed for different purposes. In this chapter, design and simulation of novel operational transconductance amplifiers (OTAs) based on carbon nanotubes (CNT) has been performed. Two structures of CNT based OTAs have been proposed and have been compared with a conventional CMOS based OTA. The two CNT based OTAs include the one employing CNT based NMOS and conventional PMOS transistors, named as NCNT-PMOS-OTA and the other employing CNT based PMOS and conventional NMOS transistors, named as PCNT-NMOS-OTA. The proposed structures are designed using HSPICE and are based on 45 nm technology node. The key characteristics of the proposed devices, like DC voltage gain, average power, bandwidth and output resistance have been computed. It has been observed that CNT based OTAs result in high performance in comparison to CMOS-OTA. The DC gain has increased by 44.4 % in PCNT-NMOS OTA and 69.3 % in NCNT-PMOS OTA in comparison to CMOS-OTA. The average power has decreased by 24.18 % in PCNT-NMOS OTA and 14.98 % in NCNT-PMOS OTA in comparison to CMOS-OTA.

Simulation Study of a Novel High Performance Oxide Engineered Schottky Collector Bipolar Transistor

The metal source/drain (MSD) Schottky barrier MOSFET offers several benefits enabling the scaling of MOSFET below 30 nm gate lengths. MSD Schottky barrier MOSFET possesses low parasitic S/D resistance, abrupt junctions that enable the scaling of the device to sub-10-nm gate lengths, superior control of leakage current due to the intrinsic Schottky potential barrier, and elimination of parasitic bipolar action. In this work, we propose a novel lateral Schottky Collector Bipolar Transistor (SCBT) employing multi zone base and multi step buried oxide has been proposed and simulated. The proposed device is simulated by using a 2D numerical simulator MEDICI. The simulation study has revealed that the proposed device with two base doping zones has ~30 % higher breakdown voltage than the conventional device. The breakdown voltage increases further and is ~75 % higher, when the number of zones in the proposed devices is increased to three. The increase in breakdown voltage can be attributed to the creation of extra electric field peaks in extended base region by multi doping zones in the base.

Charge Plasma Based Bipolar Junction Transistor on Silicon on Insulator

Charge plasma based devices are gaining interest due to various reasons, since these devices doesn’t require conventional ways of creating different doping regions, therefore these devices are free from various doping related issues related, as random doping fluctuations, doping activations and the requirement of high temperature annealing are absent in these devices. In this work we put forward a novel lateral pnp bipolar transistor on silicon on insulator. Metals of different work function are used to induce n and p type charge plasma on undoped silicon to have emitter, base and collector regions. The 2D simulation study has revealed that a very high current gain is achieved in the proposed device in comparison to conventional pnp transistor. The charge plasma concept is very much appropriate in surmounting the doping related issues such as diffusion or ion implantation, random doping fluctuations and high thermal budget in current nano devices.