Salvador Ceballos

Survey on Fault Operation on Multilevel Inverters

This paper is related to faults that can appear in multilevel (ML) inverters, which have a high number of components. This is a subject of increasing importance in high-power inverters. First, methods to identify a fault are classified and briefly described for each topology. In addition, a number of strategies and hardware modifications that allow for operation in faulty conditions are also presented. As a result of the analyzed works, it can be concluded that ML inverters can significantly increase their availability and are able to operate even with some faulty components.

A Carrier-Based PWM Strategy With Zero-Sequence Voltage Injection for a Three-Level Neutral-Point-Clamped Converter

Performance of a carrier-based pulsewidth modulation (CB-PWM) strategy can be improved by the inclusion of a zero-sequence voltage in the modulation-reference signal. This paper proposes a new CB-PWM strategy for a three-level neutral-point-clamped (NPC) converter, which is based on a zero-sequence voltage injection. By inclusion of the zero-sequence voltage, the sinusoidal-modulation reference is modified to 1) carry out the voltage-balancing task of the dc-link capacitors, with no additional control effort, 2) reduce the switching losses, and 3) reduce the low-frequency voltage oscillations of the neutral point. The proposed strategy is an alternative approach to the nearest three-vector (NTV) space-vector modulation (SVM) strategy and is obtained by the analysis of the NTV-SVM strategy and establishing a correlation between the NTV-SVM and the CB-PWM strategies. The salient features of the proposed scheme, as compared with the NTV-SVM strategy, are: 1) its reduced computational processing time which is attractive for digital implementation and 2) its reduced switching losses. Compared with the existing CB-PWM strategies, the proposed strategy offers 1) capability to balance the capacitor voltages and reduce the NP voltage oscillations and 2) reduced switching losses. Performance of the proposed CB-PWM strategy for a three-level NPC converter based on time-domain simulation studies in the MATLAB/SIMULINK environment is evaluated and also experimentally verified.

Fast-Processing Modulation Strategy for the Neutral-Point-Clamped Converter With Total Elimination of Low-Frequency Voltage Oscillations in the Neutral Point

This paper presents a novel modulation strategy for a neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based pulsewidth modulation. Nevertheless, it can generate the maximum output-voltage amplitudes that are attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm and, hence, can be processed very quickly. The only drawback of this strategy is that the switching frequencies of the devices are one third higher than those of standard sinusoidal pulsewidth modulation. A control loop for balancing the voltages on the dc-link capacitors is also proposed. This balancing strategy is designed, so that it does not further increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment.

Voltage-Balance Compensator for a Carrier-Based Modulation in the Neutral-Point-Clamped Converter

This paper presents an optimal voltage-balancing compensator for a specific modulation technique applied to a neutral-point-clamped converter. The technique uses two modulation signals per phase, and it is called double-signal pulsewidth modulation. It completely eliminates low-frequency oscillations in the neutral-point voltage. However, it does not provide natural voltage balancing; therefore, a compensation loop is required. The proposed control generates a feedback compensation signal that correctly modifies the three-phase modulation signals. The optimal compensation signal is calculated by a dynamic limiter according to the intrinsic limitations of the system related to the variability range of the modulation signals. It significantly improves the voltage balancing under all operating conditions of the converter. In addition, this compensation strategy does not increase the switching frequencies of the power devices. The algorithm is tested and verified using both simulation and experimentation.

Circulating Current Injection Methods Based on Instantaneous Information for the Modular Multilevel Converter

This paper studies different circulating current references for the modular multilevel converter. The circulating current references are obtained from the instantaneous values of the output current and modulation signal of the phase leg. Therefore, the determination of the amplitude and phase of the output current is not needed, which is a significant improvement compared to other methods such as those based on injecting specific harmonics in the circulating currents. Among the different methods studied in this paper, a new method is introduced, which is able to reduce the capacitor voltage ripples compared to the other methods. A closed-loop control is also proposed which is able to track the circulating current references. With the discussed methods, the average values of the capacitor voltages are maintained at their reference while the voltage ripples are kept low. Experimental results are presented to demonstrate the effectiveness of the proposed and discussed methods.

Three-Level Converter Topologies With Switch Breakdown Fault-Tolerance Capability

This paper presents some modified topologies of the neutral-point-clamped converter. In all of them, the main change consists of adding a fourth leg, which is based on the flying-capacitor converter structure. The aim of this additional leg is to provide the converter with fault tolerance. Furthermore, during normal operation mode, this leg is able to provide a stiff neutral voltage. Consequently, the low-frequency voltage oscillations that appear at the neutral point of the standard three-level topology in some operating conditions no longer exist. As a result, the modulation strategy of the three main legs of the converter does not have to take care of voltage balance, and it can be designed to either achieve optimal output voltage spectra or improve the efficiency of the converter. Simulation and experimental results are presented to show the viability of this approach both under normal operation mode and in the event of faults.

Variable-Frequency Grid-Sequence Detector Based on a Quasi-Ideal Low-Pass Filter Stage and a Phase-Locked Loop

This paper proposes a filtered-sequence phase-locked loop (FSPLL) structure for detection of the positive sequence in three-phase systems. The structure includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows a proper selection of the window width of the optimal filter for its application in the dq transformed variables. The proposed detector structure allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF eliminates completely any oscillation multiple of the frequency for which it is designed; thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, the PLL includes a simple-frequency detector that makes frequency adaptive the frequency depending blocks. This guarantees the proper operation of the FSPLL under large frequency changes. The performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.

Performance Evaluation of Fault-Tolerant Neutral-Point-Clamped Converters

This paper presents a study of the fault tolerance capacity of a neutral-point-clamped converter. Different faults in power semiconductors are considered, and the available postfault states of the converter are shown. In regard of the operation limits, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Furthermore, an analysis of the neutral-point voltage balancing conditions after a fault and reconfiguration of the system is also evaluated. Experimental results that prove the correct operation of the proposed topologies are shown.

Active Redundant Submodule Configuration in Modular Multilevel Converters

The modular multilevel converter (MMC) is based on the cascaded connection of identical submodules (SMs) enabling additional redundancies. This paper proposes the configuration of the MMC topology with redundant SMs and demonstrates the effects of active redundancies. The proposed configuration decreases the switching frequency per SM while reducing the SM capacitor voltage ripples. An analytical model for determining the SM capacitor voltage ripple and voltage dynamics is derived. The results from the analytical model are compared with the switching model for a 21-level MMC with five redundant (25 in total) SMs per arm. Experimental results based on a single-phase laboratory prototype with five SMs per arm and a single redundant cell further illustrate the operation and verify the derived mathematical model and simulation results.

Analysis of voltage balancing limits in modular multilevel converters

The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.