Josep Pou

Analysis of voltage balancing limits in modular multilevel converters

The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.

Minimization of the capacitor voltage fluctuations of a modular multilevel converter by circulating current control

The modular multilevel converter (MMC) is one of the most potential converter topologies for medium/high power/voltage applications. One of the main technical challenges of an MMC is to eliminate/minimize the circulating currents within the legs. Circulating currents, if not properly controlled, increase the amplitude of capacitor voltage variations, rating values of the converter components and converter losses. This paper proposes a closed-loop circulating current control strategy for an MMC to specifically minimize the amplitude of capacitor voltage variations. The proposed strategy is based on adding an offset signal to the modulating signal of each arm. To minimize the amplitude of the capacitor voltage oscillations, an optimal circulating current component is determined and used as a reference signal for the current control of each MMC leg. Performance of the proposed control strategy is evaluated based on simulation studies in the MATLAB/Simulink environment. The reported study results demonstrate effectiveness of the proposed strategy to reduce the amplitude of the capacitor voltage oscillations.

Fault-Tolerant Multilevel Converter Topology

This paper presents a modified topology of the neutral-point-clamped converter. The main change consists on adding a fourth leg, which is based on the flying-capacitor converter structure. The aim of this additional leg is to provide fault tolerance to the converter. Furthermore, during normal operation mode, this leg is able to provide a stiff neutral voltage. Consequently, the low-frequency voltage oscillations that appear in the neutral point of the standard three-level topology for some operation conditions no longer exist. As a result, the modulation strategy of the three main legs of the converter does not have to take care of voltage balance, and it can be design to achieve optimal output voltage waveforms, as well as to improve efficiency of the converter. Some simulation results are presented to show viability of this approach under both, normal operation mode and fault event. Experimental results are expected to include in the final paper.

Performance evaluation of a five-level flying capacitor converter with reduced DC bus capacitance under two different modulation schemes

A back-to-back HVDC converter system is typically used to connect two separate electrical grids or a remote large-scale renewable energy system with the electrical grid through a DC bus. The DC bus typically contains a large electrolytic capacitor giving a robust performance to the converter system. However, it is well known that the electrolytic DC bus capacitor is bulky and has a low reliability. Therefore, a possible solution to these drawbacks is to use a reduced DC bus capacitance, which will allow film capacitors to be used instead of electrolytic capacitors. This paper presents the performance evaluation of a five-level flying capacitor (FC) back-to-back converter system with reduced DC bus capacitance under different modulation schemes. Two carrier-based modulation strategies are studied, namely the phase shifted pulse-width modulation (PS-PWM) and the phase disposition pulse-width modulation (PD-PWM), along with their appropriate flying capacitor voltage balancing techniques. The classical synchronous reference frame control strategy has been implemented in order to provide DC bus voltage regulation and active/reactive power control. The performance of the two different modulation schemes is tested against the DC bus and FCs voltage ripples using the MATLAB/Simulink-PLECS software platform. The analyzed case studies demonstrate that the PS-PWM strategy is more suitable to operate the proposed FC converter system using reduced values for the DC bus and flying capacitors.

Three-Leg Fault-Tolerant Neutral-Point-Clamped Converter

This paper presents a study of the fault tolerance capacity of a neutral-point-clamped (NPC) converter. Furthermore, two possible solutions are presented. In these solutions, adding a reduced number of additional components, the behavior of the converter when a switch fails improves considerably. Simulations results that prove the correct operation of the proposed topologies are shown.

Soft-Switching Topology for a Fault-Tolerant Neutral-Point-Clamped Converter

This paper presents a new three-level topology based on the neutral-point-clamped converter. The new topology includes a fourth leg that provides fault tolerance to the converter. Furthermore, during normal operation mode, this leg is able to provide a stiff neutral voltage. Consequently, the low- frequency voltage oscillations that appear in the neutral point of the standard three-level topology for some operation conditions no longer exist. As a result, the modulation strategy of the three main legs of the converter does not have to take care of voltage balance, and it can be design to improve the efficiency of the converter. On the other hand, the addition of a fourth leg to the converter produces additional losses. However, in order to eliminate switching losses of this leg, all the power devices commutate under zero-current or zero-voltage transitions. Some simulation results are presented to show viability of this approach under both, normal operation mode and fault event.

On the use of sun trackers to improve maximum power point tracking controllers applied to photovoltaic systems

Nowadays power supply systems based on photovoltaic cells have two main drawbacks, even the primary energy is free and renewable. They are: production cost and efficiency. In order to increase their efficiency, it should be interesting that the energy transfer between cells and load was done at maximum level. In this paper the use of a sun tracker system is presented as an additional improvement applied to a photovoltaic installation that works under a maximum power point tracking (MPPT) control technique. A 50W-prototype has been assembled. Some experimental results are also included in order to validate the whole system.

Power losses calculation methodology to evaluate inverter efficiency in electrical vehicles

Nowadays, electrical vehicles (EVs) are of special interest and fuel engines are starting to be substituted by electrical motors. Besides the batteries and the motor, the power electronic devices are important parts in an EV, especially the inverter. This ac/dc power converter drives the electrical motor. Several tools may be needed to achieve an optimal design of the inverter. This paper presents a simplified methodology to estimate power losses in a two-level inverter made up with isolated gate bipolar transistors (IGBTs). This methodology is based on the IGBT manufacturer datasheet; therefore, the knowledge of internal parameters used in other more complex methodologies is not required. The model is implemented in Matlab-Simulink and allows simulation of different power devices, modulation techniques, and operating conditions very easily. Some results are obtained and validated with commercial electronic software and also with the simulation tool Semisel, provided by the manufacturer of the IGBTs.

Grid synchronization method based on a quasi-ideal low-pass filter stage and a phase-locked loop

This paper proposes a new phase-locked loop (PLL) scheme for detection of the positive sequence in three-phase systems. The scheme includes the use of the Park transformation and moving average filters (MAF). Performance of the MAF is mathematically analyzed and represented in Bode diagrams. The analysis allows proper selection of the optimal filterpsilas window width for its application in d-q transformed variables. The proposed detector scheme allows fast detection of the grid voltage positive sequence (within one grid voltage cycle). The MAF completely eliminates any oscillation multiple of the frequency for what it is designed. Thus, this algorithm is not affected by the presence of imbalances or harmonics in the electrical grid. Furthermore, although it is designed to operate under constant frequency, it can also operate properly well in the presence of small grid frequency variations. Performance of the entire PLL-based detector is verified through simulation and experiment. It shows very good performance under several extreme grid voltage conditions.

Efficient Modulation Technique for a Four-Leg Fault-Tolerant Neutral-Point-Clamped Inverter

This paper presents a new low-loss modulation technique for the hybrid three-level four-leg converter. The total losses of the converter are reduced by about 18% on average compared to the standard three-leg neutral-point-clamped converter. Furthermore, the low-frequency voltage oscillation in the neutral point is completely cancelled, and the maximum benefit of the dc-link voltage is obtained. All these facts, together with the fault-tolerant ability due to the fourth leg, make this topology very interesting for applications such as wind generation, in which it is important to maximize efficiency and reliability. Some experimental results confirm the good performance of the proposed modulation technique.