Salvatore Bellone

Switching Device Based on a Thin Film of an Azo-Containing Polymer for Application in Memory Cells

Results obtained on a conductive multilevel device realized with a 100 nm azo-polymer film are reported. The capability to switch between three different conductance states makes the device versatile both for Write Once Read Many and Write Many Read Many memory cell application. The analysis of the - curves indicates that the hysteretic conductance change with the external voltage can be explained in terms of different hopping distances existing between the nearest neighbors intervening in the two conformational states of the molecular structure.

A Self-Consistent Model of the OCVD Behavior of Si and 4H-SiC

A comprehensive analytical model of the open-circuit voltage-decay (OCVD) response for a generic diode, switched from an arbitrary forward-bias condition, is proposed. To properly account for the steady-state conditions of the diode, the dynamic model incorporates an accurate description of the static I-V curves, which turns also useful for better understanding the influence of physical parameters on voltage transitory. As shown from comparisons with simulations and experiments, the model accurately describes the spatial-temporal variation of carriers and currents along the whole epilayer and allows one to resolve some ambiguities reported in the literature, such as the stated inapplicability of the OCVD method on thick epilayers, the reasons of the observed nonlinear decay of the voltage with time, and the effects of junction properties on voltage transient.

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An electronic circuit for making accurate open-circuit voltage decay measurements is presented. The circuit overcomes the main limitations that occur in the standard method when used for carrier lifetime characterization because it realizes the ldquoopen-circuit conditionsrdquo of the device under test with an impedance higher than 100 MOmega and reduces the noise that is inherent in the differential operation of the method.

Diodes

A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed-form equations, the dc forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on set of electrothermal stability of 4H-SiC DMOSFETs both in triode and in saturation region and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014 ] cm-2 · eV-1 for operating temperatures up to 500 K. Comparisons with experimental data of 1.2 and 1.7 kV commercial devices are used to validate the model.

An Analog Circuit for Accurate OCVD Measurements

The presence of crossing points in the forward JD-VD curves of 4H-SiC pin diodes is analyzed by means of numerical and analytical models. The analysis allows one to justify the different temperature coefficients reported in the literature for SiC diodes and the interlacing behavior of their JD-VD curves. A simple formula for predicting the position of the crossing-point is proposed.

Analytical Model of the Forward Operation of 4H-SiC Vertical DMOSFET in the Safe Operating Temperature Range

In this letter, the first experimental results of a recently proposed technique for measuring the carrier lifetime profile are presented. The technique makes use of a four-terminal bipolar test structure to electrically define the epilayer volume where recombination occurs and employs the open circuit voltage decay method for lifetime parameters extraction. For the capability of the test structure to depurate measurements from the parasitic ohmic effects, the technique is able to measure the ambipolar and minority carrier lifetime along epilayer at high and low injection levels respectively. Comparisons of measurements with numerical simulations are reported to confirm the validity of the proposed technique.

On the Crossing-Point of 4H-SiC Power Diodes Characteristics

A new analytical description of the trapped charge distribution at the semiconductor-insulator interface of 4H-SiC vertical-DMOSFET has been derived as a function of the surface potential into the channel. The model allows one to accurately calculate the electrical characteristics of the device in both subthreshold and above-threshold operations, namely, when the channel works from weak accumulation to strong inversion. The accuracy of the model has been verified by comparisons with numerical simulations and with experimental measurements of a 1.7-kV commercial device.

Experimental measurements of majority and minority carrier lifetime profile in SI epilayers by the use of an improved OCVD method

The first analytical model of the transfer characteristics of normally OFF JFETs devices is presented. The model exploits an original description of carrier distributions in the channel as function of gate and drain voltages, which are then used to determine the barrier height and ID - VGS curves for a generic channel geometry and bias condition of the device. The generality of the model is proved by comparisons with numerical simulations of the barrier height and ID - VGS curves of Si and 4H-SiC JFETs, designed using different aspect ratios and doping, and with the measured ID - VGS curves of existing devices.

Modeling of the SiO 2 /SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

An original model of the potential barrier in the channel of bipolar static induction transistors (BSITs) is presented. The model allows us to evaluate the potential barrier height for an arbitrary gate topology and to accurately predict the minority and majority carrier densities at the middle of the channel for a generic gate bias. The validity of the model is verified by comparison with numerical simulations of BSIT structures reported by other authors and with original simulations carried out on silicon (Si) and silicon carbide (SiC) junction field-effect transistors.

A Model of the

An analytical instrument to design 4H-SiC planar and trenched junction barrier Schottky (JBS) diodes is proposed. The tool is based on a novel full analytical description of the electric field distribution into channel region of the device under reverse bias conditions. The model favorably exploits compact and reversible expressions that take into account all physical and geometrical quantities of the device in order to calculate the electric field at the Schottky contact as well as the reverse diode current, up to the occurrence of the physical limits of the Schottky junction. In contrast to the existing literature, the generality of the model is achieved by the absence of empirical parameters, since all the expressions are analytically derived. Finally, the capability of the analytical model to design generic JBS structures (planar, trenched, or recessed p-type regions) is shown in a step-by-step design process, too. Comparisons with numerical simulations and experimental data evidenced the high validity of the model and showed that it can be used both for high-voltage power diodes and for high switching frequency devices.