Sam Gu

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.

Multi-die chip on wafer thermo-compression bonding using non-conductive film

Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies.

Synergistic effect of electromigration and Joule heating on system level weak-link failure in 2.5D integrated circuits

In system level electromigration test of 2.5D integrated circuits, a failure mode due to synergistic effect of Joule heating and electromigration has been found. In the test circuit, there are three levels of solder joints, two Si chips (one of them has through-Si-via), and one polymer substrate. In addition, there are two redistribution layers; one between every two levels of solder joints. We found that the redistribution layer between the flip chip solder joints and micro-bumps is the weak-link and failed easily by burn-out in electromigration test. The failure is time-dependent with sudden resistance increase. Preliminary simulation results show that Joule heating has a positive feedback to electromigration in the redistribution layer and caused the thermal run-away failure. Joule heating becomes an important reliability issue in the future scaling of semiconductor devices.

Filler trap and solder extrusion in 3D IC thermo-compression bonded microbumps

As the Moores law is drawing to an end, there is a growing consensus that 3D stacking of Si integrated circuit chips is necessary to continue the current technological trend. In our work, a test 3D IC structure is successfully achieved and the effect of filler trap on microbump of solder joints will be discussed. In our test samples, the two Si chips are connected through thermo-compression bonding of 20 μm diameter microbumps. After bonding the two chips together, some underfill materials are found to stay on the interface of joining in the microbumps; the residual underfill in the microbump is defined as “filler trap”. Together with the formation of filler trap, a ring-type solder extrusion also forms on the circumference of the microbump. Although the filler trap is an electrical insulator, it has been found that the solder extrusion is a good electricity conductor. But the filler trap in solder can cause a detour of electric current path in solder. The detoured current potentially increases current crowding in the joint which might be accelerating electromigration. To investigate this potential issue, specially processed test vehicle which intentionally has higher filler traps and solder protrusion was fabricated for easier detection. The synchrotron radiation x-ray tomography results show that the solder extrusion in microbumps have a random shape, which may cause a random distribution of early failure in electromigration.

Joule Heating Enhanced Electromigration Failure in Redistribution Layer in 2.5D IC

In system level electromigration test of 2.5D IC, Joule heating enhanced electromigration failure has been found to occur in redistribution layer in the interposer. In our test samples, there are two redistribution layers (RDL), each between every two levels of solder joints, so there are three levels of solder joints. First, the microbumps connect a Si chip on top and an interposer chip in the middle. Second, the flip chip solders connect the interposer and a polymer substrate on the bottom. Third, the BGA solder balls on the back of the substrate as I/O connections to the outside. In our system level electromigration tests, a BGA ball served as the cathode and allowed electrons to flow through the circuit of path-through-holes, flip chip solder joint, TSV, and microbumps, and then to return in the opposite direction to another BGA ball as the anode. We found that the RDL between the flip chip solder joints and micro-bumps is the weak-link and failed easily by burn-out in electromigration tests. The failure is time-dependent with sudden resistance increase. Preliminary simulation results show that because of poor heat dissipation, Joule heating will accumulate, leading to temperature increase. The increased temperature has a positive feedback to enhance electromigration in the RDL and caused the thermal run-away failure.

Joule heating induced thermomigration failure in un-powered microbumps due to thermal crosstalk in 2.5D IC technology

Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si interposer was used between a polymer substrate and a device chip which has transistors. The interposer has no transistors. If transistors are added to the interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si interposer. The vertical connections between the interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chip are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchr...

Electromigration induced thermomigration in microbumps by thermal cross-talk across neighboring chips in 2.5D IC

This paper investigates the thermal cross-talk between the powered microbumps under one chip and the un-powered microbumps under the neighboring chip. Both chips were on a Si interposer for 2.5D IC. The Joule heating from the powered chip was found to be transferred laterally along the interposer to the unpowered chip and produced a temperature gradient in the microbumps in the unpowered chip. Void formation is observed in both the powered and the unpowered microbumps. The latter is due to thermomigration (TM), and the former is due to electromigration (EM). The amount of voids is bigger by TM than by EM. The void nucleation and growing is studied by examining the un-powered microbumps at different stages during electromigration tests. The nucleation of voids at the cold end in TM is observed, which indicates that Sn atoms diffuse from cold end to hot end. The current-enhanced surface electromigration of Sn along the side walls of Cu pillars to form intermetallic compound is observed in the powered microbumps that were subjected to a 5.3 × 104 A/cm2 current density at 150 °C for a period of time. The depletion of Sn will cause serious void formation in these powered microbumps.

Effect of Au/Pd surface finishing on metastable Sn phase formation in microbumps

A metastable phase of Sn has been found to co-exist with ß-Sn in Pb-free SnAg microbumps in 3D integrated circuit (3D IC) technology. Synchrotron microbeam x-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has a orthorhombic lattice, with lattice parameter a = 0.635 nm, b = 0.639 nm, and c = 1.147 nm. Its composition is Sn containing about 10 percent of Ni, a few percent of Au and Pd. The structure is probably isostructural with those of Sn4Au, and Sn4Pd with Ni replacing the noble metal. The formation of this phase may be because of Au and Pd in surface finishing for Ni. With only one reflow, this new phase could form almost continuously in microbumps solder when the thickness of solder layer shrinks to 2 μm. The formation of this phase implies the well adopted Au/Pd surface finishing structure may cause potential reliability problems in 3D IC.