Riko Radojcic

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and effcient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Network-on-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benets of such design choice.

TechTuning: Stress Management For 3D Through‐Silicon‐Via Stacking Technologies

The concerns with managing mechanical stress distributions and the consequent effects on device performance and material integrity, for advanced TSV based technologies 3D are outlined. A model and simulation based Design For Manufacturability (DFM) type of a flow for managing the mechanical stresses throughout Si die, stack and package design is proposed. The key attributes of the models and simulators required to fuel the proposed flow are summarized. Finally, some of the essential infrastructure and the Supply Chain support items are described.

Simulation methodology and flow integration for 3D IC stress management

A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations.

Multi-die chip on wafer thermo-compression bonding using non-conductive film

Advanced chip on wafer (CoW) assembly has emerged as a key assembly technology for enabling advanced silicon nodes and complex integration. Traditional assembly methods for chip attach have proven capable in this approach, but suffer in the area of fillet design rules. Non-conductive films have been in development as a replacement to the liquid pre-applied underfill materials used in fine pitch copper pillar assembly; however implementation has been slowed by unfavorable cost of ownership and low throughput. Results from recent development have proven the feasibility of a multi-die (gang) bond chip on wafer assembly process. Key assembly steps have been validated and major issues have been mitigated through optimization of materials and process parameters. A scale up phase of development has been initiated which targets the bonding of 8 die (4 units) in a chip on wafer format. The results of this scale up will help move the industry toward a process that can deliver advanced assembly design rules at a cost competitive position when compared to incumbent technologies.

Are there economic benefits in DFM

A fabless company perspective is presented on the roles of the foundries, design entities and EDA providers in the DFM arena, and the requirements for measurement of the economic benefits of DFM.

First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications

This paper reports the first demonstration of the drop-test reliability performance of large, ultra-thin glass BGA packages that are directly mounted onto the system board, unlike the current approach of flip-chip assembly of interposers, involving additional organic packages which are then SMT assembled onto boards. The packages, 18.4mm × 18.4mm in size made of 100μm-thick glass, were also successfully assembled, for the first time, in a SMT line. The effect on drop reliability of the glass BGAs with circumferential polymer collars was studied extensively. While the glass BGA packages met the reliability requirements, both with and without polymer collars, the polymer collars were found to further enhance the drop performance, as well as the fatigue life of solders. Finite element modeling was used to understand strain-relief mechanisms and provide design guidelines for reliability. The glass substrates fabrication process along with the formation of polymer collars by spin coating is detailed. The glass package-to-PCB assemblies were formed using SMT-compatible processes with standard equipment, followed by reliability testing through thermal cycling and drop tests. The compiled failure data from drop testing was fitted into a Weibull distribution plot. Comprehensive failure analysis was performed to assess the structural integrity of the glass substrates and identify the predominant failure mechanisms in drop test.

Enabling power distribution network analysis flows for 3D ICs

This paper concentrates on some of these new challenges that designers must face in power delivery. We will discuss QUALCOMMs effort with EDA vendors to develop power distribution network (PDN) analysis flows in order to address the power delivery issues in 3DICs, and emphasize the necessity of a standard reduced power model (SRPM) to enable the 3D PDN analysis flows.

Design for manufacturability for fabless manufactuers

When a company designs and sells ICs but outsources their manufacture, design for manufacturability poses special challenges. It is clear that these DfM solutions are very complex and require a series of fundamental new physical models and design practices. Practical deployment of DfM solutions requires development of an entire incremental infrastructure on both the process and design sides of the technology integration spectrum. Optimizing the various DfM methods involves complex, multi-faceted tradeoffs that are ultimately dependent on target technology and various product attributes. DfM is definitely not a one-size-fits-all panacea for all of the process manufacturability and variability challenges. Complete and successful DfM deployment is a true ecosystem that requires multiple tools using multiple models, potentially calibrated to multiple levels of accuracy, inserted at multiple points in the design flow.

Moore's Law: another casualty of the financial meltdown?

Given the exponential increase of fabrication costs, the global recession and credit crunch, one may ask if Moores law is financially viable beyond 22 nm node. Can we justify the return-of-investment (ROI) for continuous scaling beyond 22 nm? Shall we consider other alternatives for integration, such as silicon-in-a-package (SiP) or 3D integrations?